[llvm] r320732 - Add MVT::v128i1, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 11:05:22 PST 2017
Author: kparzysz
Date: Thu Dec 14 11:05:21 2017
New Revision: 320732
URL: http://llvm.org/viewvc/llvm-project?rev=320732&view=rev
Log:
Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineValueType.h
llvm/trunk/include/llvm/CodeGen/ValueTypes.td
llvm/trunk/lib/IR/ValueTypes.cpp
llvm/trunk/test/TableGen/intrinsic-varargs.td
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineValueType.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineValueType.h?rev=320732&r1=320731&r2=320732&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineValueType.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineValueType.h Thu Dec 14 11:05:21 2017
@@ -64,80 +64,81 @@ namespace llvm {
v16i1 = 18, // 16 x i1
v32i1 = 19, // 32 x i1
v64i1 = 20, // 64 x i1
- v512i1 = 21, // 512 x i1
- v1024i1 = 22, // 1024 x i1
+ v128i1 = 21, // 128 x i1
+ v512i1 = 22, // 512 x i1
+ v1024i1 = 23, // 1024 x i1
+
+ v1i8 = 24, // 1 x i8
+ v2i8 = 25, // 2 x i8
+ v4i8 = 26, // 4 x i8
+ v8i8 = 27, // 8 x i8
+ v16i8 = 28, // 16 x i8
+ v32i8 = 29, // 32 x i8
+ v64i8 = 30, // 64 x i8
+ v128i8 = 31, //128 x i8
+ v256i8 = 32, //256 x i8
+
+ v1i16 = 33, // 1 x i16
+ v2i16 = 34, // 2 x i16
+ v4i16 = 35, // 4 x i16
+ v8i16 = 36, // 8 x i16
+ v16i16 = 37, // 16 x i16
+ v32i16 = 38, // 32 x i16
+ v64i16 = 39, // 64 x i16
+ v128i16 = 40, //128 x i16
+
+ v1i32 = 41, // 1 x i32
+ v2i32 = 42, // 2 x i32
+ v4i32 = 43, // 4 x i32
+ v8i32 = 44, // 8 x i32
+ v16i32 = 45, // 16 x i32
+ v32i32 = 46, // 32 x i32
+ v64i32 = 47, // 64 x i32
+
+ v1i64 = 48, // 1 x i64
+ v2i64 = 49, // 2 x i64
+ v4i64 = 50, // 4 x i64
+ v8i64 = 51, // 8 x i64
+ v16i64 = 52, // 16 x i64
+ v32i64 = 53, // 32 x i64
- v1i8 = 23, // 1 x i8
- v2i8 = 24, // 2 x i8
- v4i8 = 25, // 4 x i8
- v8i8 = 26, // 8 x i8
- v16i8 = 27, // 16 x i8
- v32i8 = 28, // 32 x i8
- v64i8 = 29, // 64 x i8
- v128i8 = 30, //128 x i8
- v256i8 = 31, //256 x i8
-
- v1i16 = 32, // 1 x i16
- v2i16 = 33, // 2 x i16
- v4i16 = 34, // 4 x i16
- v8i16 = 35, // 8 x i16
- v16i16 = 36, // 16 x i16
- v32i16 = 37, // 32 x i16
- v64i16 = 38, // 64 x i16
- v128i16 = 39, //128 x i16
-
- v1i32 = 40, // 1 x i32
- v2i32 = 41, // 2 x i32
- v4i32 = 42, // 4 x i32
- v8i32 = 43, // 8 x i32
- v16i32 = 44, // 16 x i32
- v32i32 = 45, // 32 x i32
- v64i32 = 46, // 64 x i32
-
- v1i64 = 47, // 1 x i64
- v2i64 = 48, // 2 x i64
- v4i64 = 49, // 4 x i64
- v8i64 = 50, // 8 x i64
- v16i64 = 51, // 16 x i64
- v32i64 = 52, // 32 x i64
-
- v1i128 = 53, // 1 x i128
+ v1i128 = 54, // 1 x i128
// Scalable integer types
- nxv1i1 = 54, // n x 1 x i1
- nxv2i1 = 55, // n x 2 x i1
- nxv4i1 = 56, // n x 4 x i1
- nxv8i1 = 57, // n x 8 x i1
- nxv16i1 = 58, // n x 16 x i1
- nxv32i1 = 59, // n x 32 x i1
-
- nxv1i8 = 60, // n x 1 x i8
- nxv2i8 = 61, // n x 2 x i8
- nxv4i8 = 62, // n x 4 x i8
- nxv8i8 = 63, // n x 8 x i8
- nxv16i8 = 64, // n x 16 x i8
- nxv32i8 = 65, // n x 32 x i8
-
- nxv1i16 = 66, // n x 1 x i16
- nxv2i16 = 67, // n x 2 x i16
- nxv4i16 = 68, // n x 4 x i16
- nxv8i16 = 69, // n x 8 x i16
- nxv16i16 = 70, // n x 16 x i16
- nxv32i16 = 71, // n x 32 x i16
-
- nxv1i32 = 72, // n x 1 x i32
- nxv2i32 = 73, // n x 2 x i32
- nxv4i32 = 74, // n x 4 x i32
- nxv8i32 = 75, // n x 8 x i32
- nxv16i32 = 76, // n x 16 x i32
- nxv32i32 = 77, // n x 32 x i32
-
- nxv1i64 = 78, // n x 1 x i64
- nxv2i64 = 79, // n x 2 x i64
- nxv4i64 = 80, // n x 4 x i64
- nxv8i64 = 81, // n x 8 x i64
- nxv16i64 = 82, // n x 16 x i64
- nxv32i64 = 83, // n x 32 x i64
+ nxv1i1 = 55, // n x 1 x i1
+ nxv2i1 = 56, // n x 2 x i1
+ nxv4i1 = 57, // n x 4 x i1
+ nxv8i1 = 58, // n x 8 x i1
+ nxv16i1 = 59, // n x 16 x i1
+ nxv32i1 = 60, // n x 32 x i1
+
+ nxv1i8 = 61, // n x 1 x i8
+ nxv2i8 = 62, // n x 2 x i8
+ nxv4i8 = 63, // n x 4 x i8
+ nxv8i8 = 64, // n x 8 x i8
+ nxv16i8 = 65, // n x 16 x i8
+ nxv32i8 = 66, // n x 32 x i8
+
+ nxv1i16 = 67, // n x 1 x i16
+ nxv2i16 = 68, // n x 2 x i16
+ nxv4i16 = 69, // n x 4 x i16
+ nxv8i16 = 70, // n x 8 x i16
+ nxv16i16 = 71, // n x 16 x i16
+ nxv32i16 = 72, // n x 32 x i16
+
+ nxv1i32 = 73, // n x 1 x i32
+ nxv2i32 = 74, // n x 2 x i32
+ nxv4i32 = 75, // n x 4 x i32
+ nxv8i32 = 76, // n x 8 x i32
+ nxv16i32 = 77, // n x 16 x i32
+ nxv32i32 = 78, // n x 32 x i32
+
+ nxv1i64 = 79, // n x 1 x i64
+ nxv2i64 = 80, // n x 2 x i64
+ nxv4i64 = 81, // n x 4 x i64
+ nxv8i64 = 82, // n x 8 x i64
+ nxv16i64 = 83, // n x 16 x i64
+ nxv32i64 = 84, // n x 32 x i64
FIRST_INTEGER_VECTOR_VALUETYPE = v1i1,
LAST_INTEGER_VECTOR_VALUETYPE = nxv32i64,
@@ -145,31 +146,31 @@ namespace llvm {
FIRST_INTEGER_SCALABLE_VALUETYPE = nxv1i1,
LAST_INTEGER_SCALABLE_VALUETYPE = nxv32i64,
- v2f16 = 84, // 2 x f16
- v4f16 = 85, // 4 x f16
- v8f16 = 86, // 8 x f16
- v1f32 = 87, // 1 x f32
- v2f32 = 88, // 2 x f32
- v4f32 = 89, // 4 x f32
- v8f32 = 90, // 8 x f32
- v16f32 = 91, // 16 x f32
- v1f64 = 92, // 1 x f64
- v2f64 = 93, // 2 x f64
- v4f64 = 94, // 4 x f64
- v8f64 = 95, // 8 x f64
-
- nxv2f16 = 96, // n x 2 x f16
- nxv4f16 = 97, // n x 4 x f16
- nxv8f16 = 98, // n x 8 x f16
- nxv1f32 = 99, // n x 1 x f32
- nxv2f32 = 100, // n x 2 x f32
- nxv4f32 = 101, // n x 4 x f32
- nxv8f32 = 102, // n x 8 x f32
- nxv16f32 = 103, // n x 16 x f32
- nxv1f64 = 104, // n x 1 x f64
- nxv2f64 = 105, // n x 2 x f64
- nxv4f64 = 106, // n x 4 x f64
- nxv8f64 = 107, // n x 8 x f64
+ v2f16 = 85, // 2 x f16
+ v4f16 = 86, // 4 x f16
+ v8f16 = 87, // 8 x f16
+ v1f32 = 88, // 1 x f32
+ v2f32 = 89, // 2 x f32
+ v4f32 = 90, // 4 x f32
+ v8f32 = 91, // 8 x f32
+ v16f32 = 92, // 16 x f32
+ v1f64 = 93, // 1 x f64
+ v2f64 = 94, // 2 x f64
+ v4f64 = 95, // 4 x f64
+ v8f64 = 96, // 8 x f64
+
+ nxv2f16 = 97, // n x 2 x f16
+ nxv4f16 = 98, // n x 4 x f16
+ nxv8f16 = 99, // n x 8 x f16
+ nxv1f32 = 100, // n x 1 x f32
+ nxv2f32 = 101, // n x 2 x f32
+ nxv4f32 = 102, // n x 4 x f32
+ nxv8f32 = 103, // n x 8 x f32
+ nxv16f32 = 104, // n x 16 x f32
+ nxv1f64 = 105, // n x 1 x f64
+ nxv2f64 = 106, // n x 2 x f64
+ nxv4f64 = 107, // n x 4 x f64
+ nxv8f64 = 108, // n x 8 x f64
FIRST_FP_VECTOR_VALUETYPE = v2f16,
LAST_FP_VECTOR_VALUETYPE = nxv8f64,
@@ -180,18 +181,18 @@ namespace llvm {
FIRST_VECTOR_VALUETYPE = v1i1,
LAST_VECTOR_VALUETYPE = nxv8f64,
- x86mmx = 108, // This is an X86 MMX value
+ x86mmx = 109, // This is an X86 MMX value
- Glue = 109, // This glues nodes together during pre-RA sched
+ Glue = 110, // This glues nodes together during pre-RA sched
- isVoid = 110, // This has no value
+ isVoid = 111, // This has no value
- Untyped = 111, // This value takes a register, but has
+ Untyped = 112, // This value takes a register, but has
// unspecified type. The register class
// will be determined by the opcode.
FIRST_VALUETYPE = 1, // This is always the beginning of the list.
- LAST_VALUETYPE = 112, // This always remains at the end of the list.
+ LAST_VALUETYPE = 113, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
@@ -346,10 +347,11 @@ namespace llvm {
/// Return true if this is a 128-bit vector type.
bool is128BitVector() const {
- return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
- SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
- SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 ||
- SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
+ return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 ||
+ SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
+ SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
+ SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 ||
+ SimpleTy == MVT::v2f64);
}
/// Return true if this is a 256-bit vector type.
@@ -420,6 +422,7 @@ namespace llvm {
case v16i1:
case v32i1:
case v64i1:
+ case v128i1:
case v512i1:
case v1024i1:
case nxv1i1:
@@ -517,6 +520,7 @@ namespace llvm {
case v1024i1: return 1024;
case v512i1: return 512;
case v256i8: return 256;
+ case v128i1:
case v128i8:
case v128i16: return 128;
case v64i1:
@@ -690,6 +694,7 @@ namespace llvm {
case f128:
case ppcf128:
case i128:
+ case v128i1:
case v16i8:
case v8i16:
case v4i32:
@@ -828,6 +833,7 @@ namespace llvm {
if (NumElements == 16) return MVT::v16i1;
if (NumElements == 32) return MVT::v32i1;
if (NumElements == 64) return MVT::v64i1;
+ if (NumElements == 128) return MVT::v128i1;
if (NumElements == 512) return MVT::v512i1;
if (NumElements == 1024) return MVT::v1024i1;
break;
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.td?rev=320732&r1=320731&r2=320732&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.td (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.td Thu Dec 14 11:05:21 2017
@@ -40,110 +40,111 @@ def v8i1 : ValueType<8 , 17>; //
def v16i1 : ValueType<16, 18>; // 16 x i1 vector value
def v32i1 : ValueType<32 , 19>; // 32 x i1 vector value
def v64i1 : ValueType<64 , 20>; // 64 x i1 vector value
-def v512i1 : ValueType<512, 21>; // 512 x i1 vector value
-def v1024i1: ValueType<1024,22>; //1024 x i1 vector value
-
-def v1i8 : ValueType<8, 23>; // 1 x i8 vector value
-def v2i8 : ValueType<16 , 24>; // 2 x i8 vector value
-def v4i8 : ValueType<32 , 25>; // 4 x i8 vector value
-def v8i8 : ValueType<64 , 26>; // 8 x i8 vector value
-def v16i8 : ValueType<128, 27>; // 16 x i8 vector value
-def v32i8 : ValueType<256, 28>; // 32 x i8 vector value
-def v64i8 : ValueType<512, 29>; // 64 x i8 vector value
-def v128i8 : ValueType<1024,30>; //128 x i8 vector value
-def v256i8 : ValueType<2048,31>; //256 x i8 vector value
-
-def v1i16 : ValueType<16 , 32>; // 1 x i16 vector value
-def v2i16 : ValueType<32 , 33>; // 2 x i16 vector value
-def v4i16 : ValueType<64 , 34>; // 4 x i16 vector value
-def v8i16 : ValueType<128, 35>; // 8 x i16 vector value
-def v16i16 : ValueType<256, 36>; // 16 x i16 vector value
-def v32i16 : ValueType<512, 37>; // 32 x i16 vector value
-def v64i16 : ValueType<1024,38>; // 64 x i16 vector value
-def v128i16: ValueType<2048,39>; //128 x i16 vector value
-
-def v1i32 : ValueType<32 , 40>; // 1 x i32 vector value
-def v2i32 : ValueType<64 , 41>; // 2 x i32 vector value
-def v4i32 : ValueType<128, 42>; // 4 x i32 vector value
-def v8i32 : ValueType<256, 43>; // 8 x i32 vector value
-def v16i32 : ValueType<512, 44>; // 16 x i32 vector value
-def v32i32 : ValueType<1024,45>; // 32 x i32 vector value
-def v64i32 : ValueType<2048,46>; // 32 x i32 vector value
-
-def v1i64 : ValueType<64 , 47>; // 1 x i64 vector value
-def v2i64 : ValueType<128, 48>; // 2 x i64 vector value
-def v4i64 : ValueType<256, 49>; // 4 x i64 vector value
-def v8i64 : ValueType<512, 50>; // 8 x i64 vector value
-def v16i64 : ValueType<1024,51>; // 16 x i64 vector value
-def v32i64 : ValueType<2048,52>; // 32 x i64 vector value
-
-def v1i128 : ValueType<128, 53>; // 1 x i128 vector value
-
-def nxv1i1 : ValueType<1, 54>; // n x 1 x i1 vector value
-def nxv2i1 : ValueType<2, 55>; // n x 2 x i1 vector value
-def nxv4i1 : ValueType<4, 56>; // n x 4 x i1 vector value
-def nxv8i1 : ValueType<8, 57>; // n x 8 x i1 vector value
-def nxv16i1 : ValueType<16, 58>; // n x 16 x i1 vector value
-def nxv32i1 : ValueType<32, 59>; // n x 32 x i1 vector value
-
-def nxv1i8 : ValueType<8, 60>; // n x 1 x i8 vector value
-def nxv2i8 : ValueType<16, 61>; // n x 2 x i8 vector value
-def nxv4i8 : ValueType<32, 62>; // n x 4 x i8 vector value
-def nxv8i8 : ValueType<64, 63>; // n x 8 x i8 vector value
-def nxv16i8 : ValueType<128, 64>; // n x 16 x i8 vector value
-def nxv32i8 : ValueType<256, 65>; // n x 32 x i8 vector value
-
-def nxv1i16 : ValueType<16, 66>; // n x 1 x i16 vector value
-def nxv2i16 : ValueType<32, 67>; // n x 2 x i16 vector value
-def nxv4i16 : ValueType<64, 68>; // n x 4 x i16 vector value
-def nxv8i16 : ValueType<128, 69>; // n x 8 x i16 vector value
-def nxv16i16: ValueType<256, 70>; // n x 16 x i16 vector value
-def nxv32i16: ValueType<512, 71>; // n x 32 x i16 vector value
-
-def nxv1i32 : ValueType<32, 72>; // n x 1 x i32 vector value
-def nxv2i32 : ValueType<64, 73>; // n x 2 x i32 vector value
-def nxv4i32 : ValueType<128, 74>; // n x 4 x i32 vector value
-def nxv8i32 : ValueType<256, 75>; // n x 8 x i32 vector value
-def nxv16i32: ValueType<512, 76>; // n x 16 x i32 vector value
-def nxv32i32: ValueType<1024,77>; // n x 32 x i32 vector value
-
-def nxv1i64 : ValueType<64, 78>; // n x 1 x i64 vector value
-def nxv2i64 : ValueType<128, 79>; // n x 2 x i64 vector value
-def nxv4i64 : ValueType<256, 80>; // n x 4 x i64 vector value
-def nxv8i64 : ValueType<512, 81>; // n x 8 x i64 vector value
-def nxv16i64: ValueType<1024,82>; // n x 16 x i64 vector value
-def nxv32i64: ValueType<2048,83>; // n x 32 x i64 vector value
-
-def v2f16 : ValueType<32 , 84>; // 2 x f16 vector value
-def v4f16 : ValueType<64 , 85>; // 4 x f16 vector value
-def v8f16 : ValueType<128, 86>; // 8 x f16 vector value
-def v1f32 : ValueType<32 , 87>; // 1 x f32 vector value
-def v2f32 : ValueType<64 , 88>; // 2 x f32 vector value
-def v4f32 : ValueType<128, 89>; // 4 x f32 vector value
-def v8f32 : ValueType<256, 90>; // 8 x f32 vector value
-def v16f32 : ValueType<512, 91>; // 16 x f32 vector value
-def v1f64 : ValueType<64, 92>; // 1 x f64 vector value
-def v2f64 : ValueType<128, 93>; // 2 x f64 vector value
-def v4f64 : ValueType<256, 94>; // 4 x f64 vector value
-def v8f64 : ValueType<512, 95>; // 8 x f64 vector value
-
-def nxv2f16 : ValueType<32 , 96>; // n x 2 x f16 vector value
-def nxv4f16 : ValueType<64 , 97>; // n x 4 x f16 vector value
-def nxv8f16 : ValueType<128, 98>; // n x 8 x f16 vector value
-def nxv1f32 : ValueType<32 , 99>; // n x 1 x f32 vector value
-def nxv2f32 : ValueType<64 , 100>; // n x 2 x f32 vector value
-def nxv4f32 : ValueType<128, 101>; // n x 4 x f32 vector value
-def nxv8f32 : ValueType<256, 102>; // n x 8 x f32 vector value
-def nxv16f32 : ValueType<512, 103>; // n x 16 x f32 vector value
-def nxv1f64 : ValueType<64, 104>; // n x 1 x f64 vector value
-def nxv2f64 : ValueType<128, 105>; // n x 2 x f64 vector value
-def nxv4f64 : ValueType<256, 106>; // n x 4 x f64 vector value
-def nxv8f64 : ValueType<512, 107>; // n x 8 x f64 vector value
-
-def x86mmx : ValueType<64 , 108>; // X86 MMX value
-def FlagVT : ValueType<0 , 109>; // Pre-RA sched glue
-def isVoid : ValueType<0 , 110>; // Produces no value
-def untyped: ValueType<8 , 111>; // Produces an untyped value
+def v128i1 : ValueType<128, 21>; // 128 x i1 vector value
+def v512i1 : ValueType<512, 22>; // 512 x i1 vector value
+def v1024i1: ValueType<1024,23>; //1024 x i1 vector value
+
+def v1i8 : ValueType<8, 24>; // 1 x i8 vector value
+def v2i8 : ValueType<16 , 25>; // 2 x i8 vector value
+def v4i8 : ValueType<32 , 26>; // 4 x i8 vector value
+def v8i8 : ValueType<64 , 27>; // 8 x i8 vector value
+def v16i8 : ValueType<128, 28>; // 16 x i8 vector value
+def v32i8 : ValueType<256, 29>; // 32 x i8 vector value
+def v64i8 : ValueType<512, 30>; // 64 x i8 vector value
+def v128i8 : ValueType<1024,31>; //128 x i8 vector value
+def v256i8 : ValueType<2048,32>; //256 x i8 vector value
+
+def v1i16 : ValueType<16 , 33>; // 1 x i16 vector value
+def v2i16 : ValueType<32 , 34>; // 2 x i16 vector value
+def v4i16 : ValueType<64 , 35>; // 4 x i16 vector value
+def v8i16 : ValueType<128, 36>; // 8 x i16 vector value
+def v16i16 : ValueType<256, 37>; // 16 x i16 vector value
+def v32i16 : ValueType<512, 38>; // 32 x i16 vector value
+def v64i16 : ValueType<1024,39>; // 64 x i16 vector value
+def v128i16: ValueType<2048,40>; //128 x i16 vector value
+
+def v1i32 : ValueType<32 , 41>; // 1 x i32 vector value
+def v2i32 : ValueType<64 , 42>; // 2 x i32 vector value
+def v4i32 : ValueType<128, 43>; // 4 x i32 vector value
+def v8i32 : ValueType<256, 44>; // 8 x i32 vector value
+def v16i32 : ValueType<512, 45>; // 16 x i32 vector value
+def v32i32 : ValueType<1024,46>; // 32 x i32 vector value
+def v64i32 : ValueType<2048,47>; // 32 x i32 vector value
+
+def v1i64 : ValueType<64 , 48>; // 1 x i64 vector value
+def v2i64 : ValueType<128, 49>; // 2 x i64 vector value
+def v4i64 : ValueType<256, 50>; // 4 x i64 vector value
+def v8i64 : ValueType<512, 51>; // 8 x i64 vector value
+def v16i64 : ValueType<1024,52>; // 16 x i64 vector value
+def v32i64 : ValueType<2048,53>; // 32 x i64 vector value
+
+def v1i128 : ValueType<128, 54>; // 1 x i128 vector value
+
+def nxv1i1 : ValueType<1, 55>; // n x 1 x i1 vector value
+def nxv2i1 : ValueType<2, 56>; // n x 2 x i1 vector value
+def nxv4i1 : ValueType<4, 57>; // n x 4 x i1 vector value
+def nxv8i1 : ValueType<8, 58>; // n x 8 x i1 vector value
+def nxv16i1 : ValueType<16, 59>; // n x 16 x i1 vector value
+def nxv32i1 : ValueType<32, 60>; // n x 32 x i1 vector value
+
+def nxv1i8 : ValueType<8, 61>; // n x 1 x i8 vector value
+def nxv2i8 : ValueType<16, 62>; // n x 2 x i8 vector value
+def nxv4i8 : ValueType<32, 63>; // n x 4 x i8 vector value
+def nxv8i8 : ValueType<64, 64>; // n x 8 x i8 vector value
+def nxv16i8 : ValueType<128, 65>; // n x 16 x i8 vector value
+def nxv32i8 : ValueType<256, 66>; // n x 32 x i8 vector value
+
+def nxv1i16 : ValueType<16, 67>; // n x 1 x i16 vector value
+def nxv2i16 : ValueType<32, 68>; // n x 2 x i16 vector value
+def nxv4i16 : ValueType<64, 69>; // n x 4 x i16 vector value
+def nxv8i16 : ValueType<128, 70>; // n x 8 x i16 vector value
+def nxv16i16: ValueType<256, 71>; // n x 16 x i16 vector value
+def nxv32i16: ValueType<512, 72>; // n x 32 x i16 vector value
+
+def nxv1i32 : ValueType<32, 73>; // n x 1 x i32 vector value
+def nxv2i32 : ValueType<64, 74>; // n x 2 x i32 vector value
+def nxv4i32 : ValueType<128, 75>; // n x 4 x i32 vector value
+def nxv8i32 : ValueType<256, 76>; // n x 8 x i32 vector value
+def nxv16i32: ValueType<512, 77>; // n x 16 x i32 vector value
+def nxv32i32: ValueType<1024,78>; // n x 32 x i32 vector value
+
+def nxv1i64 : ValueType<64, 79>; // n x 1 x i64 vector value
+def nxv2i64 : ValueType<128, 80>; // n x 2 x i64 vector value
+def nxv4i64 : ValueType<256, 81>; // n x 4 x i64 vector value
+def nxv8i64 : ValueType<512, 82>; // n x 8 x i64 vector value
+def nxv16i64: ValueType<1024,83>; // n x 16 x i64 vector value
+def nxv32i64: ValueType<2048,84>; // n x 32 x i64 vector value
+
+def v2f16 : ValueType<32 , 85>; // 2 x f16 vector value
+def v4f16 : ValueType<64 , 86>; // 4 x f16 vector value
+def v8f16 : ValueType<128, 87>; // 8 x f16 vector value
+def v1f32 : ValueType<32 , 88>; // 1 x f32 vector value
+def v2f32 : ValueType<64 , 89>; // 2 x f32 vector value
+def v4f32 : ValueType<128, 90>; // 4 x f32 vector value
+def v8f32 : ValueType<256, 91>; // 8 x f32 vector value
+def v16f32 : ValueType<512, 92>; // 16 x f32 vector value
+def v1f64 : ValueType<64, 93>; // 1 x f64 vector value
+def v2f64 : ValueType<128, 94>; // 2 x f64 vector value
+def v4f64 : ValueType<256, 95>; // 4 x f64 vector value
+def v8f64 : ValueType<512, 96>; // 8 x f64 vector value
+
+def nxv2f16 : ValueType<32 , 97>; // n x 2 x f16 vector value
+def nxv4f16 : ValueType<64 , 98>; // n x 4 x f16 vector value
+def nxv8f16 : ValueType<128, 99>; // n x 8 x f16 vector value
+def nxv1f32 : ValueType<32 , 100>; // n x 1 x f32 vector value
+def nxv2f32 : ValueType<64 , 101>; // n x 2 x f32 vector value
+def nxv4f32 : ValueType<128, 102>; // n x 4 x f32 vector value
+def nxv8f32 : ValueType<256, 103>; // n x 8 x f32 vector value
+def nxv16f32 : ValueType<512, 104>; // n x 16 x f32 vector value
+def nxv1f64 : ValueType<64, 105>; // n x 1 x f64 vector value
+def nxv2f64 : ValueType<128, 106>; // n x 2 x f64 vector value
+def nxv4f64 : ValueType<256, 107>; // n x 4 x f64 vector value
+def nxv8f64 : ValueType<512, 108>; // n x 8 x f64 vector value
+
+def x86mmx : ValueType<64 , 109>; // X86 MMX value
+def FlagVT : ValueType<0 , 110>; // Pre-RA sched glue
+def isVoid : ValueType<0 , 111>; // Produces no value
+def untyped: ValueType<8 , 112>; // Produces an untyped value
def token : ValueType<0 , 248>; // TokenTy
def MetadataVT: ValueType<0, 249>; // Metadata
Modified: llvm/trunk/lib/IR/ValueTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/ValueTypes.cpp?rev=320732&r1=320731&r2=320732&view=diff
==============================================================================
--- llvm/trunk/lib/IR/ValueTypes.cpp (original)
+++ llvm/trunk/lib/IR/ValueTypes.cpp Thu Dec 14 11:05:21 2017
@@ -148,6 +148,7 @@ std::string EVT::getEVTString() const {
case MVT::v16i1: return "v16i1";
case MVT::v32i1: return "v32i1";
case MVT::v64i1: return "v64i1";
+ case MVT::v128i1: return "v128i1";
case MVT::v512i1: return "v512i1";
case MVT::v1024i1: return "v1024i1";
case MVT::v1i8: return "v1i8";
@@ -227,6 +228,7 @@ Type *EVT::getTypeForEVT(LLVMContext &Co
case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16);
case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32);
case MVT::v64i1: return VectorType::get(Type::getInt1Ty(Context), 64);
+ case MVT::v128i1: return VectorType::get(Type::getInt1Ty(Context), 128);
case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512);
case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024);
case MVT::v1i8: return VectorType::get(Type::getInt8Ty(Context), 1);
Modified: llvm/trunk/test/TableGen/intrinsic-varargs.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/intrinsic-varargs.td?rev=320732&r1=320731&r2=320732&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/intrinsic-varargs.td (original)
+++ llvm/trunk/test/TableGen/intrinsic-varargs.td Thu Dec 14 11:05:21 2017
@@ -23,7 +23,7 @@ class Intrinsic<string name, list<LLVMTy
}
// isVoid needs to match the definition in ValueTypes.td
-def isVoid : ValueType<0, 110>; // Produces no value
+def isVoid : ValueType<0, 111>; // Produces no value
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
// CHECK: /* 0 */ 0, 29, 0,
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=320732&r1=320731&r2=320732&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Dec 14 11:05:21 2017
@@ -82,6 +82,7 @@ StringRef llvm::getEnumName(MVT::SimpleV
case MVT::v16i1: return "MVT::v16i1";
case MVT::v32i1: return "MVT::v32i1";
case MVT::v64i1: return "MVT::v64i1";
+ case MVT::v128i1: return "MVT::v128i1";
case MVT::v512i1: return "MVT::v512i1";
case MVT::v1024i1: return "MVT::v1024i1";
case MVT::v1i8: return "MVT::v1i8";
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