[llvm] r320692 - Inserting several lit tests to reflect current behaviour
Omer Paparo Bivas via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 14 04:00:04 PST 2017
Author: opaparo
Date: Thu Dec 14 04:00:04 2017
New Revision: 320692
URL: http://llvm.org/viewvc/llvm-project?rev=320692&view=rev
Log:
Inserting several lit tests to reflect current behaviour
Change-Id: I1b8188dc3c6c7c0f455715364ece7d35ef485f2f
Added:
llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
Modified:
llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll
Modified: llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll?rev=320692&r1=320691&r2=320692&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/or-shifted-masks.ll Thu Dec 14 04:00:04 2017
@@ -131,3 +131,91 @@ define i32 @multiuse3(i32 %x) {
ret i32 %10
}
+define i32 @multiuse4(i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @multiuse4(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 100663296
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
+; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
+; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP1]], 22
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 %x, 22
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 480
+; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: [[TMP7:%.*]] = lshr exact i32 [[TMP1]], 17
+; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 %x, 17
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 15360
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}end{{.*}}
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: ret i32 [[TMP11]]
+;
+ %1 = and i32 %x, 100663296
+ %2 = icmp sgt i32 %x, -1
+ br i1 %2, label %if, label %else
+
+if:
+ %3 = lshr exact i32 %1, 22
+ %4 = lshr i32 %x, 22
+ %5 = and i32 %4, 480
+ %6 = or i32 %5, %3
+ br label %end
+
+else:
+ %7 = lshr exact i32 %1, 17
+ %8 = lshr i32 %x, 17
+ %9 = and i32 %8, 15360
+ %10 = or i32 %9, %7
+ br label %end
+
+end:
+ %11 = phi i32 [ %6, %if ], [ %10, %else ]
+ ret i32 %11
+}
+
+define i32 @multiuse5(i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @multiuse5(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 %x, -1
+; CHECK-NEXT: br i1 [[TMP2]], label %if, label %else
+; CHECK: {{.*}}if:{{.*}}
+; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 21760
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 43520
+; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP3]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}else:{{.*}}
+; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP1]], 5570560
+; CHECK-NEXT: [[TMP8:%.*]] = shl i32 %x, 5
+; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 11141120
+; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP7]]
+; CHECK-NEXT: br label %end
+; CHECK: {{.*}}end{{.*}}
+; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[TMP6]], %if ], [ [[TMP10]], %else ]
+; CHECK-NEXT: ret i32 [[TMP11]]
+;
+ %1 = shl i32 %x, 5
+ %2 = icmp sgt i32 %x, -1
+ br i1 %2, label %if, label %else
+
+if:
+ %3 = and i32 %1, 21760
+ %4 = and i32 %x, 1360
+ %5 = shl nuw nsw i32 %4, 5
+ %6 = or i32 %5, %3
+ br label %end
+
+else:
+ %7 = and i32 %1, 5570560
+ %8 = and i32 %x, 348160
+ %9 = shl nuw nsw i32 %8, 5
+ %10 = or i32 %9, %7
+ br label %end
+
+end:
+ %11 = phi i32 [ %6, %if ], [ %10, %else ]
+ ret i32 %11
+}
+
Added: llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll?rev=320692&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll Thu Dec 14 04:00:04 2017
@@ -0,0 +1,110 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 15
+; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
+; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 %y, [[TMP5]]
+; CHECK-NEXT: ret i64 [[TMP6]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 %y, [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 15
+ %2 = shl nuw nsw i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 60
+; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
+; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 %y, [[TMP5]]
+; CHECK-NEXT: ret i64 [[TMP6]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 %x, 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 %y, [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, 60
+ %2 = lshr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, -2147483588
+; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
+; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 %y, [[TMP5]]
+; CHECK-NEXT: ret i64 [[TMP6]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %1, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
+define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
+; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 %x, 2
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 %y, [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = and i32 %x, -2147483588
+ %2 = ashr i32 %1, 2
+ %3 = zext i32 %2 to i64
+ %4 = icmp eq i32 %2, 0
+ %5 = ashr i64 %y, %3
+ %6 = select i1 %4, i64 %y, i64 %5
+ ret i64 %6
+}
+
More information about the llvm-commits
mailing list