[PATCH] D41216: [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Thanks, this is a good fix. As a nitpick I'd put the UImmLog2XLenNonZeroAsmOperand and uimmlog2xlennonzero defs exactly where uimm5nonzero was in RISCVInstrInfoC.td, this retains sorting by bitwidth.


Repository:
  rL LLVM

https://reviews.llvm.org/D41216