[PATCH] D41175: [X86][AVX512F_128]: Adding full coverage of MC encoding for the AVX512F_128 isa sets.<NFC>

Gadi Haber via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 14 00:15:20 PST 2017

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gadi.haber added a comment.

AVX512F 128N are vector instructions which have a GPR or a memory with the size of a scalar as an operand (insert/extract/mov).


Repository:
  rL LLVM

https://reviews.llvm.org/D41175

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