[PATCH] D41174: [X86][AVX512F_SCALAR]: Adding full coverage of MC encoding for the AVX512F_SCALAR isa sets.<NFC>
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 13 14:05:38 PST 2017
craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.
================
Comment at: test/MC/X86/AVX512F_SCALAR-32.s:4
+// CHECK: vaddsd -485498096(%edx,%eax,4), %xmm1, %xmm1
+// CHECK: encoding: [0xc5,0xf3,0x58,0x8c,0x82,0x10,0xe3,0x0f,0xe3]
+vaddsd -485498096(%edx,%eax,4), %xmm1, %xmm1
----------------
This is a VEX encoding so this is testing AVX1. Not sure how to trick 32-bit mode to use EVEX for the unmasked instructions since you can't use the extended registers.
Repository:
rL LLVM
https://reviews.llvm.org/D41174
More information about the llvm-commits
mailing list