[llvm] r320575 - [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools

[Alex Bradbury via llvm-commits]

Author: asb
Date: Wed Dec 13 04:46:55 2017
New Revision: 320575

URL: http://llvm.org/viewvc/llvm-project?rev=320575&view=rev
Log:
[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools

Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/trunk/test/MC/RISCV/priv-invalid.s
    llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=320575&r1=320574&r2=320575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Dec 13 04:46:55 2017
@@ -459,6 +459,9 @@ def : InstAlias<"csrwi $csr, $imm", (CSR
 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
 
+def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
+def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
+
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //

Modified: llvm/trunk/test/MC/RISCV/priv-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/priv-invalid.s?rev=320575&r1=320574&r2=320575&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/priv-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/priv-invalid.s Wed Dec 13 04:46:55 2017
@@ -2,6 +2,6 @@
 
 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
 
-sfence.vma zero # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
 
 sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s?rev=320575&r1=320574&r2=320575&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s Wed Dec 13 04:46:55 2017
@@ -136,3 +136,10 @@ csrsi 0xfff, 0x10
 # CHECK-INST: csrrci zero, 320, 17
 # CHECK-ALIAS: csrci 320, 17
 csrci 0x140, 0x11
+
+# CHECK-INST: sfence.vma zero, zero
+# CHECK-ALIAS: sfence.vma
+sfence.vma
+# CHECK-INST: sfence.vma a0, zero
+# CHECK-ALIAS: sfence.vma a0
+sfence.vma a0