[PATCH] D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I

[Alex Bradbury via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL320487: [RISCV] Implement assembler pseudo instructions for RV32I and RV64I (authored by asb, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D40902?vs=126370&id=126549#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D40902

Files:
  llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
  llvm/trunk/lib/Target/RISCV/RISCV.td
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s
  llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s
  llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
  llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s

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