[llvm] r320459 - [X86] Use Ld scheduler classes for instructions with folded loads.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 23:06:35 PST 2017
Author: ctopper
Date: Mon Dec 11 23:06:35 2017
New Revision: 320459
URL: http://llvm.org/viewvc/llvm-project?rev=320459&view=rev
Log:
[X86] Use Ld scheduler classes for instructions with folded loads.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrFMA.td
llvm/trunk/lib/Target/X86/X86InstrXOP.td
llvm/trunk/test/CodeGen/X86/fma-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=320459&r1=320458&r2=320459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Dec 11 23:06:35 2017
@@ -6037,7 +6037,7 @@ multiclass avx512_fma3p_213_rm<bits<8> o
(ins _.RC:$src2, _.MemOp:$src3),
OpcodeStr, "$src3, $src2", "$src2, $src3",
(_.VT (OpNode _.RC:$src2, _.RC:$src1, (_.LdFrag addr:$src3))),
- NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMA, ReadAfterLd]>;
+ NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>;
defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.ScalarMemOp:$src3),
@@ -6046,7 +6046,7 @@ multiclass avx512_fma3p_213_rm<bits<8> o
(OpNode _.RC:$src2,
_.RC:$src1,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))),
NoItinerary, 1, 0>, AVX512FMA3Base, EVEX_B,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
}
@@ -6105,7 +6105,7 @@ multiclass avx512_fma3p_231_rm<bits<8> o
(ins _.RC:$src2, _.MemOp:$src3),
OpcodeStr, "$src3, $src2", "$src2, $src3",
(_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)),
- NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMA, ReadAfterLd]>;
+ NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>;
defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.ScalarMemOp:$src3),
@@ -6114,7 +6114,7 @@ multiclass avx512_fma3p_231_rm<bits<8> o
(_.VT (OpNode _.RC:$src2,
(_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
_.RC:$src1)), NoItinerary, 1, 0>, AVX512FMA3Base, EVEX_B,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
}
@@ -6175,7 +6175,7 @@ multiclass avx512_fma3p_132_rm<bits<8> o
(ins _.RC:$src2, _.MemOp:$src3),
OpcodeStr, "$src3, $src2", "$src2, $src3",
(_.VT (OpNode (_.LdFrag addr:$src3), _.RC:$src1, _.RC:$src2)),
- NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMA, ReadAfterLd]>;
+ NoItinerary, 1, 0>, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>;
// Pattern is 312 order so that the load is in a different place from the
// 213 and 231 patterns this helps tablegen's duplicate pattern detection.
@@ -6185,7 +6185,7 @@ multiclass avx512_fma3p_132_rm<bits<8> o
"$src2, ${src3}"##_.BroadcastStr,
(_.VT (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
_.RC:$src1, _.RC:$src2)), NoItinerary, 1, 0>,
- AVX512FMA3Base, EVEX_B, Sched<[WriteFMA, ReadAfterLd]>;
+ AVX512FMA3Base, EVEX_B, Sched<[WriteFMALd, ReadAfterLd]>;
}
}
@@ -6244,7 +6244,7 @@ let Constraints = "$src1 = $dst", hasSid
defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
"$src3, $src2", "$src2, $src3", RHS_VEC_m, NoItinerary, 1, 1>,
- AVX512FMA3Base, Sched<[WriteFMA, ReadAfterLd]>;
+ AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>;
defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
@@ -6262,7 +6262,7 @@ let Constraints = "$src1 = $dst", hasSid
(ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [RHS_m]>, Sched<[WriteFMA, ReadAfterLd]>;
+ [RHS_m]>, Sched<[WriteFMALd, ReadAfterLd]>;
}// isCodeGenOnly = 1
}// Constraints = "$src1 = $dst"
}
Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=320459&r1=320458&r2=320459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Mon Dec 11 23:06:35 2017
@@ -51,7 +51,7 @@ multiclass fma3p_rm_213<bits<8> opc, str
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
(MemFrag addr:$src3))))]>,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
multiclass fma3p_rm_231<bits<8> opc, string OpcodeStr, RegisterClass RC,
@@ -70,7 +70,7 @@ multiclass fma3p_rm_231<bits<8> opc, str
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst, (VT (Op RC:$src2, (MemFrag addr:$src3),
- RC:$src1)))]>, Sched<[WriteFMA, ReadAfterLd]>;
+ RC:$src1)))]>, Sched<[WriteFMALd, ReadAfterLd]>;
}
multiclass fma3p_rm_132<bits<8> opc, string OpcodeStr, RegisterClass RC,
@@ -91,7 +91,7 @@ multiclass fma3p_rm_132<bits<8> opc, str
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst, (VT (Op (MemFrag addr:$src3), RC:$src1,
- RC:$src2)))]>, Sched<[WriteFMA, ReadAfterLd]>;
+ RC:$src2)))]>, Sched<[WriteFMALd, ReadAfterLd]>;
}
let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in
@@ -184,7 +184,7 @@ multiclass fma3s_rm_213<bits<8> opc, str
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
(OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
multiclass fma3s_rm_231<bits<8> opc, string OpcodeStr,
@@ -204,7 +204,7 @@ multiclass fma3s_rm_231<bits<8> opc, str
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
(OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
multiclass fma3s_rm_132<bits<8> opc, string OpcodeStr,
@@ -226,7 +226,7 @@ multiclass fma3s_rm_132<bits<8> opc, str
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
(OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
}
let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in
@@ -270,7 +270,7 @@ multiclass fma3s_rm_int<bits<8> opc, str
(ins RC:$src1, RC:$src2, memopr:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- []>, Sched<[WriteFMA, ReadAfterLd]>;
+ []>, Sched<[WriteFMALd, ReadAfterLd]>;
}
// The FMA 213 form is created for lowering of scalar FMA intrinscis
@@ -374,14 +374,14 @@ multiclass fma4s<bits<8> opc, string Opc
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (OpNode RC:$src1, RC:$src2,
(mem_frag addr:$src3)))]>, VEX_W, VEX_LIG,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
def mr : FMA4S<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst,
(OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst),
@@ -407,14 +407,14 @@ let isCodeGenOnly = 1 in {
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst, (VT (OpNode VR128:$src1, VR128:$src2,
mem_cpat:$src3)))]>, VEX_W, VEX_LIG,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
def mr_Int : FMA4S_Int<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, memop:$src2, VR128:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst,
(VT (OpNode VR128:$src1, mem_cpat:$src2, VR128:$src3)))]>,
- VEX_LIG, Sched<[WriteFMA, ReadAfterLd]>;
+ VEX_LIG, Sched<[WriteFMALd, ReadAfterLd]>;
let hasSideEffects = 0 in
def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
@@ -441,14 +441,14 @@ multiclass fma4p<bits<8> opc, string Opc
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
(ld_frag128 addr:$src3)))]>, VEX_W,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, f128mem:$src2, VR128:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst,
(OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
let isCommutable = 1 in
def Yrr : FMA4<opc, MRMSrcRegOp4, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, VR256:$src3),
@@ -463,14 +463,14 @@ multiclass fma4p<bits<8> opc, string Opc
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
(ld_frag256 addr:$src3)))]>, VEX_W, VEX_L,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
def Ymr : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f256mem:$src2, VR256:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR256:$dst, (OpNode VR256:$src1,
(ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L,
- Sched<[WriteFMA, ReadAfterLd]>;
+ Sched<[WriteFMALd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
Modified: llvm/trunk/lib/Target/X86/X86InstrXOP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrXOP.td?rev=320459&r1=320458&r2=320459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrXOP.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrXOP.td Mon Dec 11 23:06:35 2017
@@ -18,7 +18,7 @@ multiclass xop2op<bits<8> opc, string Op
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
- Sched<[WritePHAdd, ReadAfterLd]>;
+ Sched<[WritePHAddLd, ReadAfterLd]>;
}
let ExeDomain = SSEPackedInt in {
@@ -48,7 +48,7 @@ multiclass xop2opsld<bits<8> opc, string
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP,
- Sched<[WriteFAdd, ReadAfterLd]>;
+ Sched<[WriteFAddLd, ReadAfterLd]>;
}
multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
@@ -59,7 +59,7 @@ multiclass xop2op128<bits<8> opc, string
def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
- Sched<[WriteFAdd, ReadAfterLd]>;
+ Sched<[WriteFAddLd, ReadAfterLd]>;
}
multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
@@ -70,7 +70,7 @@ multiclass xop2op256<bits<8> opc, string
def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L,
- Sched<[WriteFAdd, ReadAfterLd]>;
+ Sched<[WriteFAddLd, ReadAfterLd]>;
}
let ExeDomain = SSEPackedSingle in {
@@ -101,14 +101,14 @@ multiclass xop3op<bits<8> opc, string Op
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1),
(vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
- XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>;
+ XOP_4V, VEX_W, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
def mr : IXOP<opc, MRMSrcMem4VOp3, (outs VR128:$dst),
(ins i128mem:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
(vt128 VR128:$src2))))]>,
- XOP, Sched<[WriteVarVecShift, ReadAfterLd]>;
+ XOP, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
@@ -146,7 +146,7 @@ multiclass xop3opimm<bits<8> opc, string
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst,
(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>,
- XOP, Sched<[WriteVecShift, ReadAfterLd]>;
+ XOP, Sched<[WriteVecShiftLd, ReadAfterLd]>;
}
let ExeDomain = SSEPackedInt in {
@@ -172,7 +172,7 @@ multiclass xop4opm2<bits<8> opc, string
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set VR128:$dst,
(Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
- VR128:$src3))]>, XOP_4V, Sched<[WriteVecIMul, ReadAfterLd]>;
+ VR128:$src3))]>, XOP_4V, Sched<[WriteVecIMulLd, ReadAfterLd]>;
}
let ExeDomain = SSEPackedInt in {
@@ -221,7 +221,7 @@ multiclass xopvpcom<bits<8> opc, string
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
imm:$cc)))]>,
- XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
+ XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
!strconcat("vpcom${cc}", Suffix,
@@ -230,19 +230,19 @@ multiclass xopvpcom<bits<8> opc, string
(vt128 (OpNode (vt128 VR128:$src1),
(vt128 (bitconvert (loadv2i64 addr:$src2))),
imm:$cc)))]>,
- XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
+ XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
let isAsmParserOnly = 1, hasSideEffects = 0 in {
def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
!strconcat("vpcom", Suffix,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
- []>, XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
+ []>, XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
let mayLoad = 1 in
def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
!strconcat("vpcom", Suffix,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
- []>, XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
+ []>, XOP_4V, Sched<[WriteVecALULd, ReadAfterLd]>;
}
}
@@ -274,7 +274,7 @@ multiclass xop4op<bits<8> opc, string Op
[(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
(vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
- XOP_4V, VEX_W, Sched<[WriteShuffle, ReadAfterLd]>;
+ XOP_4V, VEX_W, Sched<[WriteShuffleLd, ReadAfterLd]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, VR128:$src3),
!strconcat(OpcodeStr,
@@ -282,7 +282,7 @@ multiclass xop4op<bits<8> opc, string Op
[(set VR128:$dst,
(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
(vt128 VR128:$src3))))]>,
- XOP_4V, Sched<[WriteShuffle, ReadAfterLd]>;
+ XOP_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
@@ -312,14 +312,14 @@ multiclass xop4op_int<bits<8> opc, strin
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
(X86andnp (load addr:$src3), RC:$src2))))]>,
- XOP_4V, VEX_W, Sched<[WriteShuffle, ReadAfterLd]>;
+ XOP_4V, VEX_W, Sched<[WriteShuffleLd, ReadAfterLd]>;
def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
(X86andnp RC:$src3, (load addr:$src2)))))]>,
- XOP_4V, Sched<[WriteShuffle, ReadAfterLd]>;
+ XOP_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs RC:$dst),
@@ -353,7 +353,7 @@ multiclass xop_vpermil2<bits<8> Opc, str
(VT (X86vpermil2 RC:$src1, RC:$src2,
(bitconvert (IntLdFrag addr:$src3)),
(i8 imm:$src4))))]>, VEX_W,
- Sched<[WriteFShuffle, ReadAfterLd]>;
+ Sched<[WriteFShuffleLd, ReadAfterLd]>;
def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
!strconcat(OpcodeStr,
@@ -361,7 +361,7 @@ multiclass xop_vpermil2<bits<8> Opc, str
[(set RC:$dst,
(VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
RC:$src3, (i8 imm:$src4))))]>,
- Sched<[WriteFShuffle, ReadAfterLd]>;
+ Sched<[WriteFShuffleLd, ReadAfterLd]>;
// For disassembler
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst),
Modified: llvm/trunk/test/CodeGen/X86/fma-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=320459&r1=320458&r2=320459&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fma-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fma-schedule.ll Mon Dec 11 23:06:35 2017
@@ -19,7 +19,7 @@ define <2 x double> @test_vfmadd213pd(<2
; GENERIC-LABEL: test_vfmadd213pd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213pd:
@@ -67,7 +67,7 @@ define <4 x double> @test_vfmadd213pd_ym
; GENERIC-LABEL: test_vfmadd213pd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213pd_ymm:
@@ -115,7 +115,7 @@ define <4 x float> @test_vfmadd213ps(<4
; GENERIC-LABEL: test_vfmadd213ps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213ps:
@@ -163,7 +163,7 @@ define <8 x float> @test_vfmadd213ps_ymm
; GENERIC-LABEL: test_vfmadd213ps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213ps_ymm:
@@ -211,7 +211,7 @@ define <2 x double> @test_vfmadd213sd(<2
; GENERIC-LABEL: test_vfmadd213sd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213sd:
@@ -259,7 +259,7 @@ define <4 x float> @test_vfmadd213ss(<4
; GENERIC-LABEL: test_vfmadd213ss:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmadd213ss:
@@ -319,7 +319,7 @@ define <2 x double> @test_vfmaddsubpd(<2
; GENERIC-LABEL: test_vfmaddsubpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmaddsubpd:
@@ -367,7 +367,7 @@ define <4 x double> @test_vfmaddsubpd_ym
; GENERIC-LABEL: test_vfmaddsubpd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmaddsubpd_ymm:
@@ -415,7 +415,7 @@ define <4 x float> @test_vfmaddsubps(<4
; GENERIC-LABEL: test_vfmaddsubps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmaddsubps:
@@ -463,7 +463,7 @@ define <8 x float> @test_vfmaddsubps_ymm
; GENERIC-LABEL: test_vfmaddsubps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmaddsubps_ymm:
@@ -523,7 +523,7 @@ define <2 x double> @test_vfmsubaddpd(<2
; GENERIC-LABEL: test_vfmsubaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsubaddpd:
@@ -571,7 +571,7 @@ define <4 x double> @test_vfmsubaddpd_ym
; GENERIC-LABEL: test_vfmsubaddpd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsubaddpd_ymm:
@@ -619,7 +619,7 @@ define <4 x float> @test_vfmsubaddps(<4
; GENERIC-LABEL: test_vfmsubaddps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsubaddps:
@@ -667,7 +667,7 @@ define <8 x float> @test_vfmsubaddps_ymm
; GENERIC-LABEL: test_vfmsubaddps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsubaddps_ymm:
@@ -727,7 +727,7 @@ define <2 x double> @test_vfmsub213pd(<2
; GENERIC-LABEL: test_vfmsub213pd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213pd:
@@ -775,7 +775,7 @@ define <4 x double> @test_vfmsub213pd_ym
; GENERIC-LABEL: test_vfmsub213pd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213pd_ymm:
@@ -823,7 +823,7 @@ define <4 x float> @test_vfmsub213ps(<4
; GENERIC-LABEL: test_vfmsub213ps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213ps:
@@ -871,7 +871,7 @@ define <8 x float> @test_vfmsub213ps_ymm
; GENERIC-LABEL: test_vfmsub213ps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213ps_ymm:
@@ -919,7 +919,7 @@ define <2 x double> @test_vfmsub213sd(<2
; GENERIC-LABEL: test_vfmsub213sd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213sd:
@@ -967,7 +967,7 @@ define <4 x float> @test_vfmsub213ss(<4
; GENERIC-LABEL: test_vfmsub213ss:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfmsub213ss:
@@ -1027,7 +1027,7 @@ define <2 x double> @test_vfnmadd213pd(<
; GENERIC-LABEL: test_vfnmadd213pd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213pd:
@@ -1075,7 +1075,7 @@ define <4 x double> @test_vfnmadd213pd_y
; GENERIC-LABEL: test_vfnmadd213pd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213pd_ymm:
@@ -1123,7 +1123,7 @@ define <4 x float> @test_vfnmadd213ps(<4
; GENERIC-LABEL: test_vfnmadd213ps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213ps:
@@ -1171,7 +1171,7 @@ define <8 x float> @test_vfnmadd213ps_ym
; GENERIC-LABEL: test_vfnmadd213ps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213ps_ymm:
@@ -1219,7 +1219,7 @@ define <2 x double> @test_vfnmadd213sd(<
; GENERIC-LABEL: test_vfnmadd213sd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213sd:
@@ -1267,7 +1267,7 @@ define <4 x float> @test_vfnmadd213ss(<4
; GENERIC-LABEL: test_vfnmadd213ss:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmadd213ss:
@@ -1327,7 +1327,7 @@ define <2 x double> @test_vfnmsub213pd(<
; GENERIC-LABEL: test_vfnmsub213pd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213pd:
@@ -1375,7 +1375,7 @@ define <4 x double> @test_vfnmsub213pd_y
; GENERIC-LABEL: test_vfnmsub213pd_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213pd_ymm:
@@ -1423,7 +1423,7 @@ define <4 x float> @test_vfnmsub213ps(<4
; GENERIC-LABEL: test_vfnmsub213ps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213ps:
@@ -1471,7 +1471,7 @@ define <8 x float> @test_vfnmsub213ps_ym
; GENERIC-LABEL: test_vfnmsub213ps_ymm:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213ps_ymm:
@@ -1519,7 +1519,7 @@ define <2 x double> @test_vfnmsub213sd(<
; GENERIC-LABEL: test_vfnmsub213sd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213sd:
@@ -1567,7 +1567,7 @@ define <4 x float> @test_vfnmsub213ss(<4
; GENERIC-LABEL: test_vfnmsub213ss:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [5:0.50]
-; GENERIC-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [5:0.50]
+; GENERIC-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_vfnmsub213ss:
More information about the llvm-commits
mailing list