[llvm] r320404 - [Hexagon] Add support for Hexagon V65
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 10:57:55 PST 2017
Author: kparzysz
Date: Mon Dec 11 10:57:54 2017
New Revision: 320404
URL: http://llvm.org/viewvc/llvm-project?rev=320404&view=rev
Log:
[Hexagon] Add support for Hexagon V65
Added:
llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h
llvm/trunk/lib/Target/Hexagon/HexagonGatherPacketize.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV65.td
llvm/trunk/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td
llvm/trunk/lib/Target/Hexagon/HexagonPatternsV65.td
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV65.td
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/v65.ll
llvm/trunk/test/MC/Hexagon/hvx-double-implies-hvx.s
llvm/trunk/test/MC/Hexagon/v65_all.s
llvm/trunk/test/MC/Hexagon/vpred_defs.s
llvm/trunk/test/MC/Hexagon/vscatter-slot.s
llvm/trunk/test/MC/Hexagon/vtmp_def.s
Modified:
llvm/trunk/include/llvm/BinaryFormat/ELF.h
llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/trunk/lib/Target/Hexagon/Hexagon.td
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td
llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td
llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td
llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h
llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td
llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td
llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
llvm/trunk/test/MC/Hexagon/PacketRules/endloop_branches.s
llvm/trunk/test/MC/Hexagon/new-value-check.s
llvm/trunk/test/MC/Hexagon/v60-misc.s
Modified: llvm/trunk/include/llvm/BinaryFormat/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BinaryFormat/ELF.h?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BinaryFormat/ELF.h (original)
+++ llvm/trunk/include/llvm/BinaryFormat/ELF.h Mon Dec 11 10:57:54 2017
@@ -584,6 +584,7 @@ enum {
EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55
EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60
EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62
+ EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65
// Highest ISA version flags
EF_HEXAGON_ISA_MACH = 0x00000000, // Same as specified in bits[11:0]
@@ -595,6 +596,7 @@ enum {
EF_HEXAGON_ISA_V55 = 0x00000050, // Hexagon V55 ISA
EF_HEXAGON_ISA_V60 = 0x00000060, // Hexagon V60 ISA
EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA
+ EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA
};
// Hexagon-specific section indexes for common small data
Modified: llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsHexagon.td Mon Dec 11 10:57:54 2017
@@ -5044,7 +5044,6 @@ def int_hexagon_V6_vassignp_128B :
Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">;
-
//
// Hexagon_iii_Intrinsic<string GCCIntSuffix>
// tag : S6_rol_i_r
@@ -5583,54 +5582,6 @@ class Hexagon_v1024i_Intrinsic<string GC
[IntrNoMem]>;
//
-// Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb
-class Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
-// Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb_128B
-class Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
-// Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb_acc
-class Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
-// Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb_acc_128B
-class Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
-// Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb_dv_128B
-class Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
-// Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix>
-// tag : V6_vlutb_dv_acc_128B
-class Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix>
- : Hexagon_Intrinsic<GCCIntSuffix,
- [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty],
- [IntrNoMem]>;
-
-//
// Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
// tag : V6_vlutvvb_oracc
class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix>
@@ -9167,54 +9118,6 @@ def int_hexagon_V6_vcombine_128B :
Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">;
//
-// BUILTIN_INFO(HEXAGON.V6_vlutb,VI_ftype_VIDISI,3)
-// tag : V6_vlutb
-def int_hexagon_V6_vlutb :
-Hexagon_v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_128B,VI_ftype_VIDISI,3)
-// tag : V6_vlutb_128B
-def int_hexagon_V6_vlutb_128B :
-Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_128B">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_acc,VI_ftype_VIVIDISI,4)
-// tag : V6_vlutb_acc
-def int_hexagon_V6_vlutb_acc :
-Hexagon_v512v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb_acc">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_acc_128B,VI_ftype_VIVIDISI,4)
-// tag : V6_vlutb_acc_128B
-def int_hexagon_V6_vlutb_acc_128B :
-Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_acc_128B">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv,VD_ftype_VDDISI,3)
-// tag : V6_vlutb_dv
-def int_hexagon_V6_vlutb_dv :
-Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_128B,VD_ftype_VDDISI,3)
-// tag : V6_vlutb_dv_128B
-def int_hexagon_V6_vlutb_dv_128B :
-Hexagon_v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_128B">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc,VD_ftype_VDVDDISI,4)
-// tag : V6_vlutb_dv_acc
-def int_hexagon_V6_vlutb_dv_acc :
-Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc">;
-
-//
-// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc_128B,VD_ftype_VDVDDISI,4)
-// tag : V6_vlutb_dv_acc_128B
-def int_hexagon_V6_vlutb_dv_acc_128B :
-Hexagon_v2048v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc_128B">;
-
-//
// BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2)
// tag : V6_vdelta
def int_hexagon_V6_vdelta :
@@ -9349,6 +9252,30 @@ Hexagon_v2048v2048v1024v1024i_Intrinsic<
//
// Masked vector stores
//
+def int_hexagon_V6_vS32b_qpred_ai :
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
+
+def int_hexagon_V6_vS32b_nqpred_ai :
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
+
+def int_hexagon_V6_vS32b_nt_qpred_ai :
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
+
+def int_hexagon_V6_vS32b_nt_nqpred_ai :
+Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
+
+def int_hexagon_V6_vS32b_qpred_ai_128B :
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
+
+def int_hexagon_V6_vS32b_nqpred_ai_128B :
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
+
+def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
+
+def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
+Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
+
def int_hexagon_V6_vmaskedstoreq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
@@ -9642,6 +9569,20 @@ class Hexagon_V62_v2048v2048v1024v1024i_
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
+// Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
+// tag: V6_vaddcarry
+class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
+ [IntrNoMem]>;
+
+// Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
+// tag: V6_vaddcarry_128B
+class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
+ [IntrNoMem]>;
+
//
// BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)
@@ -10213,3 +10154,821 @@ Hexagon_V62_v1024v512v512i_Intrinsic<"HE
def int_hexagon_V6_vlutvwh_nm_128B :
Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
+//
+// BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3)
+// tag: V6_vaddcarry
+def int_hexagon_V6_vaddcarry :
+Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3)
+// tag: V6_vaddcarry_128B
+def int_hexagon_V6_vaddcarry_128B :
+Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3)
+// tag: V6_vsubcarry
+def int_hexagon_V6_vsubcarry :
+Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3)
+// tag: V6_vsubcarry_128B
+def int_hexagon_V6_vsubcarry_128B :
+Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">;
+
+
+///
+/// HexagonV65 intrinsics
+///
+
+//
+// Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
+// tag : A6_vcmpbeq_notany
+class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vrmpyub_rtt
+class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vrmpyub_rtt_128B
+class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vrmpyub_rtt_acc
+class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vrmpyub_rtt_acc_128B
+class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vasruwuhsat
+class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vasruwuhsat_128B
+class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
+// tag : V6_vavguw
+class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
+// tag : V6_vavguw_128B
+class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
+// tag : V6_vabsb
+class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
+// tag : V6_vabsb_128B
+class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpabuu
+class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpabuu_128B
+class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpabuu_acc_128B
+class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpyh_acc
+class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpyh_acc_128B
+class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpahhsat
+class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpahhsat_128B
+class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vlut4
+class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
+// tag : V6_vlut4_128B
+class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vmpyuhe
+class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vprefixqb
+class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v16i32_ty], [llvm_v512i1_ty],
+ [IntrNoMem]>;
+
+//
+// Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
+// tag : V6_vprefixqb_128B
+class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v32i32_ty], [llvm_v1024i1_ty],
+ [IntrNoMem]>;
+
+//
+// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2)
+// tag : A6_vcmpbeq_notany
+def int_hexagon_A6_vcmpbeq_notany :
+Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
+
+//
+// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2)
+// tag : A6_vcmpbeq_notany_128B
+def int_hexagon_A6_vcmpbeq_notany_128B :
+Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2)
+// tag : V6_vrmpyub_rtt
+def int_hexagon_V6_vrmpyub_rtt :
+Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2)
+// tag : V6_vrmpyub_rtt_128B
+def int_hexagon_V6_vrmpyub_rtt_128B :
+Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3)
+// tag : V6_vrmpyub_rtt_acc
+def int_hexagon_V6_vrmpyub_rtt_acc :
+Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3)
+// tag : V6_vrmpyub_rtt_acc_128B
+def int_hexagon_V6_vrmpyub_rtt_acc_128B :
+Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2)
+// tag : V6_vrmpybub_rtt
+def int_hexagon_V6_vrmpybub_rtt :
+Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2)
+// tag : V6_vrmpybub_rtt_128B
+def int_hexagon_V6_vrmpybub_rtt_128B :
+Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3)
+// tag : V6_vrmpybub_rtt_acc
+def int_hexagon_V6_vrmpybub_rtt_acc :
+Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3)
+// tag : V6_vrmpybub_rtt_acc_128B
+def int_hexagon_V6_vrmpybub_rtt_acc_128B :
+Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3)
+// tag : V6_vasruwuhsat
+def int_hexagon_V6_vasruwuhsat :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3)
+// tag : V6_vasruwuhsat_128B
+def int_hexagon_V6_vasruwuhsat_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3)
+// tag : V6_vasruhubsat
+def int_hexagon_V6_vasruhubsat :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3)
+// tag : V6_vasruhubsat_128B
+def int_hexagon_V6_vasruhubsat_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3)
+// tag : V6_vasruhubrndsat
+def int_hexagon_V6_vasruhubrndsat :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3)
+// tag : V6_vasruhubrndsat_128B
+def int_hexagon_V6_vasruhubrndsat_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3)
+// tag : V6_vaslh_acc
+def int_hexagon_V6_vaslh_acc :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3)
+// tag : V6_vaslh_acc_128B
+def int_hexagon_V6_vaslh_acc_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3)
+// tag : V6_vasrh_acc
+def int_hexagon_V6_vasrh_acc :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3)
+// tag : V6_vasrh_acc_128B
+def int_hexagon_V6_vasrh_acc_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2)
+// tag : V6_vavguw
+def int_hexagon_V6_vavguw :
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2)
+// tag : V6_vavguw_128B
+def int_hexagon_V6_vavguw_128B :
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2)
+// tag : V6_vavguwrnd
+def int_hexagon_V6_vavguwrnd :
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2)
+// tag : V6_vavguwrnd_128B
+def int_hexagon_V6_vavguwrnd_128B :
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2)
+// tag : V6_vavgb
+def int_hexagon_V6_vavgb :
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2)
+// tag : V6_vavgb_128B
+def int_hexagon_V6_vavgb_128B :
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2)
+// tag : V6_vavgbrnd
+def int_hexagon_V6_vavgbrnd :
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2)
+// tag : V6_vavgbrnd_128B
+def int_hexagon_V6_vavgbrnd_128B :
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2)
+// tag : V6_vnavgb
+def int_hexagon_V6_vnavgb :
+Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2)
+// tag : V6_vnavgb_128B
+def int_hexagon_V6_vnavgb_128B :
+Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1)
+// tag : V6_vabsb
+def int_hexagon_V6_vabsb :
+Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1)
+// tag : V6_vabsb_128B
+def int_hexagon_V6_vabsb_128B :
+Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1)
+// tag : V6_vabsb_sat
+def int_hexagon_V6_vabsb_sat :
+Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1)
+// tag : V6_vabsb_sat_128B
+def int_hexagon_V6_vabsb_sat_128B :
+Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2)
+// tag : V6_vmpabuu
+def int_hexagon_V6_vmpabuu :
+Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2)
+// tag : V6_vmpabuu_128B
+def int_hexagon_V6_vmpabuu_128B :
+Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3)
+// tag : V6_vmpabuu_acc
+def int_hexagon_V6_vmpabuu_acc :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3)
+// tag : V6_vmpabuu_acc_128B
+def int_hexagon_V6_vmpabuu_acc_128B :
+Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3)
+// tag : V6_vmpyh_acc
+def int_hexagon_V6_vmpyh_acc :
+Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3)
+// tag : V6_vmpyh_acc_128B
+def int_hexagon_V6_vmpyh_acc_128B :
+Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3)
+// tag : V6_vmpahhsat
+def int_hexagon_V6_vmpahhsat :
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3)
+// tag : V6_vmpahhsat_128B
+def int_hexagon_V6_vmpahhsat_128B :
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3)
+// tag : V6_vmpauhuhsat
+def int_hexagon_V6_vmpauhuhsat :
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3)
+// tag : V6_vmpauhuhsat_128B
+def int_hexagon_V6_vmpauhuhsat_128B :
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3)
+// tag : V6_vmpsuhuhsat
+def int_hexagon_V6_vmpsuhuhsat :
+Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3)
+// tag : V6_vmpsuhuhsat_128B
+def int_hexagon_V6_vmpsuhuhsat_128B :
+Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2)
+// tag : V6_vlut4
+def int_hexagon_V6_vlut4 :
+Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2)
+// tag : V6_vlut4_128B
+def int_hexagon_V6_vlut4_128B :
+Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2)
+// tag : V6_vmpyuhe
+def int_hexagon_V6_vmpyuhe :
+Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2)
+// tag : V6_vmpyuhe_128B
+def int_hexagon_V6_vmpyuhe_128B :
+Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3)
+// tag : V6_vmpyuhe_acc
+def int_hexagon_V6_vmpyuhe_acc :
+Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3)
+// tag : V6_vmpyuhe_acc_128B
+def int_hexagon_V6_vmpyuhe_acc_128B :
+Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1)
+// tag : V6_vprefixqb
+def int_hexagon_V6_vprefixqb :
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1)
+// tag : V6_vprefixqb_128B
+def int_hexagon_V6_vprefixqb_128B :
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1)
+// tag : V6_vprefixqh
+def int_hexagon_V6_vprefixqh :
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1)
+// tag : V6_vprefixqh_128B
+def int_hexagon_V6_vprefixqh_128B :
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1)
+// tag : V6_vprefixqw
+def int_hexagon_V6_vprefixqw :
+Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1)
+// tag : V6_vprefixqw_128B
+def int_hexagon_V6_vprefixqw_128B :
+Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
+
+
+// The scatter/gather ones below will not be generated from iset.py. Make sure
+// you don't overwrite these.
+class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
+ llvm_v16i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
+ llvm_v32i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
+ llvm_v64i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v16i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v32i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v32i32_ty],
+ [IntrArgMemOnly]>;
+
+class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v64i32_ty],
+ [IntrArgMemOnly]>;
+
+def int_hexagon_V6_vgathermw :
+Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
+
+def int_hexagon_V6_vgathermw_128B :
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
+
+def int_hexagon_V6_vgathermh :
+Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
+
+def int_hexagon_V6_vgathermh_128B :
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
+
+def int_hexagon_V6_vgathermhw :
+Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
+
+def int_hexagon_V6_vgathermhw_128B :
+Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
+
+def int_hexagon_V6_vgathermwq :
+Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
+
+def int_hexagon_V6_vgathermwq_128B :
+Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
+
+def int_hexagon_V6_vgathermhq :
+Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
+
+def int_hexagon_V6_vgathermhq_128B :
+Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
+
+def int_hexagon_V6_vgathermhwq :
+Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
+
+def int_hexagon_V6_vgathermhwq_128B :
+Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
+
+class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_i32_ty,llvm_i32_ty,
+ llvm_v16i32_ty,llvm_v16i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_i32_ty,llvm_i32_ty,
+ llvm_v32i32_ty,llvm_v32i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_v512i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v16i32_ty,
+ llvm_v16i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_v1024i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v32i32_ty,
+ llvm_v32i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_i32_ty,llvm_i32_ty,
+ llvm_v32i32_ty,llvm_v16i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_i32_ty,llvm_i32_ty,
+ llvm_v64i32_ty,llvm_v32i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_v512i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v32i32_ty,
+ llvm_v16i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [], [llvm_v1024i1_ty,llvm_i32_ty,
+ llvm_i32_ty,llvm_v64i32_ty,
+ llvm_v32i32_ty],
+ [IntrWriteMem]>;
+
+class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
+ : Hexagon_Intrinsic<GCCIntSuffix,
+ [llvm_v64i32_ty], [],
+ [IntrNoMem]>;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermw
+def int_hexagon_V6_vscattermw :
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermw_128B
+def int_hexagon_V6_vscattermw_128B :
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermh
+def int_hexagon_V6_vscattermh :
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermh_128B
+def int_hexagon_V6_vscattermh_128B :
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermw_add
+def int_hexagon_V6_vscattermw_add :
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermw_add_128B
+def int_hexagon_V6_vscattermw_add_128B :
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermh_add
+def int_hexagon_V6_vscattermh_add :
+Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
+// tag : V6_vscattermh_add_128B
+def int_hexagon_V6_vscattermh_add_128B :
+Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
+// tag : V6_vscattermwq
+def int_hexagon_V6_vscattermwq :
+Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
+// tag : V6_vscattermwq_128B
+def int_hexagon_V6_vscattermwq_128B :
+Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
+// tag : V6_vscattermhq
+def int_hexagon_V6_vscattermhq :
+Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
+// tag : V6_vscattermhq_128B
+def int_hexagon_V6_vscattermhq_128B :
+Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
+// tag : V6_vscattermhw
+def int_hexagon_V6_vscattermhw :
+Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
+// tag : V6_vscattermhw_128B
+def int_hexagon_V6_vscattermhw_128B :
+Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
+// tag : V6_vscattermhwq
+def int_hexagon_V6_vscattermhwq :
+Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
+// tag : V6_vscattermhwq_128B
+def int_hexagon_V6_vscattermhwq_128B :
+Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
+// tag : V6_vscattermhw_add
+def int_hexagon_V6_vscattermhw_add :
+Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
+// tag : V6_vscattermhw_add_128B
+def int_hexagon_V6_vscattermhw_add_128B :
+Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0)
+// tag : V6_vdd0
+def int_hexagon_V6_vdd0 :
+Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">;
+
+//
+// BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0)
+// tag : V6_vdd0_128B
+def int_hexagon_V6_vdd0_128B :
+Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">;
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Mon Dec 11 10:57:54 2017
@@ -47,6 +47,7 @@
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
+#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
@@ -60,9 +61,6 @@
using namespace llvm;
-static cl::opt<bool> EnableFutureRegs("mfuture-regs",
- cl::desc("Enable future registers"));
-
static cl::opt<bool> WarnMissingParenthesis(
"mwarn-missing-parenthesis",
cl::desc("Warn for missing parenthesis around predicate registers"),
@@ -95,12 +93,20 @@ class HexagonAsmParser : public MCTarget
}
MCAsmParser &Parser;
- MCAssembler *Assembler;
MCInst MCB;
bool InBrackets;
MCAsmParser &getParser() const { return Parser; }
- MCAssembler *getAssembler() const { return Assembler; }
+ MCAssembler *getAssembler() const {
+ MCAssembler *Assembler = nullptr;
+ // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
+ if (!Parser.getStreamer().hasRawTextSupport()) {
+ MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
+ Assembler = &MES->getAssembler();
+ }
+ return Assembler;
+ }
+
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
bool equalIsAsmAssignment() override { return false; }
@@ -123,7 +129,7 @@ class HexagonAsmParser : public MCTarget
bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
OperandVector &InstOperands, uint64_t &ErrorInfo,
bool MatchingInlineAsm);
-
+ void eatToEndOfPacket();
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -155,17 +161,11 @@ public:
HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
- MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
+ InBrackets(false) {
+ MCB.setOpcode(Hexagon::BUNDLE);
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
MCAsmParserExtension::Initialize(_Parser);
-
- Assembler = nullptr;
- // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
- if (!Parser.getStreamer().hasRawTextSupport()) {
- MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
- Assembler = &MES->getAssembler();
- }
}
bool splitIdentifier(OperandVector &Operands);
@@ -190,6 +190,7 @@ public:
/// instruction.
struct HexagonOperand : public MCParsedAsmOperand {
enum KindTy { Token, Immediate, Register } Kind;
+ MCContext &Context;
SMLoc StartLoc, EndLoc;
@@ -216,10 +217,12 @@ struct HexagonOperand : public MCParsedA
struct ImmTy Imm;
};
- HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
+ HexagonOperand(KindTy K, MCContext &Context)
+ : MCParsedAsmOperand(), Kind(K), Context(Context) {}
public:
- HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
+ HexagonOperand(const HexagonOperand &o)
+ : MCParsedAsmOperand(), Context(o.Context) {
Kind = o.Kind;
StartLoc = o.StartLoc;
EndLoc = o.EndLoc;
@@ -392,9 +395,13 @@ public:
return;
}
int64_t Extended = SignExtend64(Value, 32);
+ HexagonMCExpr *NewExpr = HexagonMCExpr::create(
+ MCConstantExpr::create(Extended, Context), Context);
if ((Extended < 0) != (Value < 0))
- Expr->setSignMismatch();
- Inst.addOperand(MCOperand::createExpr(Expr));
+ NewExpr->setSignMismatch();
+ NewExpr->setMustExtend(Expr->mustExtend());
+ NewExpr->setMustNotExtend(Expr->mustNotExtend());
+ Inst.addOperand(MCOperand::createExpr(NewExpr));
}
void addn1ConstOperands(MCInst &Inst, unsigned N) const {
@@ -408,8 +415,9 @@ public:
void print(raw_ostream &OS) const override;
- static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
- HexagonOperand *Op = new HexagonOperand(Token);
+ static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
+ StringRef Str, SMLoc S) {
+ HexagonOperand *Op = new HexagonOperand(Token, Context);
Op->Tok.Data = Str.data();
Op->Tok.Length = Str.size();
Op->StartLoc = S;
@@ -417,18 +425,18 @@ public:
return std::unique_ptr<HexagonOperand>(Op);
}
- static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
- SMLoc E) {
- HexagonOperand *Op = new HexagonOperand(Register);
+ static std::unique_ptr<HexagonOperand>
+ CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
+ HexagonOperand *Op = new HexagonOperand(Register, Context);
Op->Reg.RegNum = RegNum;
Op->StartLoc = S;
Op->EndLoc = E;
return std::unique_ptr<HexagonOperand>(Op);
}
- static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
- SMLoc E) {
- HexagonOperand *Op = new HexagonOperand(Immediate);
+ static std::unique_ptr<HexagonOperand>
+ CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
+ HexagonOperand *Op = new HexagonOperand(Immediate, Context);
Op->Imm.Val = Val;
Op->StartLoc = S;
Op->EndLoc = E;
@@ -480,8 +488,8 @@ bool HexagonAsmParser::finishBundle(SMLo
// 4 or less we have a packet that is too big.
if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
Error(IDLoc, "invalid instruction packet: out of slots");
- return true; // Error
}
+ return true; // Error
}
return false; // No error
@@ -493,13 +501,23 @@ bool HexagonAsmParser::matchBundleOption
if (!Parser.getTok().is(AsmToken::Colon))
return false;
Lex();
+ char const *MemNoShuffMsg =
+ "invalid instruction packet: mem_noshuf specifier not "
+ "supported with this architecture";
StringRef Option = Parser.getTok().getString();
+ auto IDLoc = Parser.getTok().getLoc();
if (Option.compare_lower("endloop0") == 0)
HexagonMCInstrInfo::setInnerLoop(MCB);
else if (Option.compare_lower("endloop1") == 0)
HexagonMCInstrInfo::setOuterLoop(MCB);
+ else if (Option.compare_lower("mem_noshuf") == 0)
+ if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
+ HexagonMCInstrInfo::setMemReorderDisabled(MCB);
+ else
+ return getParser().Error(IDLoc, MemNoShuffMsg);
else
- return true;
+ return getParser().Error(IDLoc, llvm::Twine("'") + Option +
+ "' is not a valid bundle option");
Lex();
}
}
@@ -512,13 +530,13 @@ void HexagonAsmParser::canonicalizeImmed
NewInst.setOpcode(MCI.getOpcode());
for (MCOperand &I : MCI)
if (I.isImm()) {
- int64_t Value (I.getImm());
+ int64_t Value(I.getImm());
NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
MCConstantExpr::create(Value, getContext()), getContext())));
} else {
if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
WarnSignedMismatch)
- Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
+ Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
NewInst.addOperand(I);
}
MCI = NewInst;
@@ -572,6 +590,15 @@ bool HexagonAsmParser::matchOneInstructi
llvm_unreachable("Implement any new match types added!");
}
+void HexagonAsmParser::eatToEndOfPacket() {
+ assert(InBrackets);
+ MCAsmLexer &Lexer = getLexer();
+ while (!Lexer.is(AsmToken::RCurly))
+ Lexer.Lex();
+ Lexer.Lex();
+ InBrackets = false;
+}
+
bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
@@ -586,6 +613,7 @@ bool HexagonAsmParser::MatchAndEmitInstr
assert(Operands.size() == 1 && "Brackets should be by themselves");
if (InBrackets) {
getParser().Error(IDLoc, "Already in a packet");
+ InBrackets = false;
return true;
}
InBrackets = true;
@@ -604,8 +632,11 @@ bool HexagonAsmParser::MatchAndEmitInstr
}
MCInst *SubInst = new (getParser().getContext()) MCInst;
if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
- MatchingInlineAsm))
+ MatchingInlineAsm)) {
+ if (InBrackets)
+ eatToEndOfPacket();
return true;
+ }
HexagonMCInstrInfo::extendIfNeeded(
getParser().getContext(), MII, MCB, *SubInst);
MCB.addOperand(MCOperand::createInst(SubInst));
@@ -853,10 +884,11 @@ bool HexagonAsmParser::splitIdentifier(O
do {
std::pair<StringRef, StringRef> HeadTail = String.split('.');
if (!HeadTail.first.empty())
- Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
+ Operands.push_back(
+ HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
if (!HeadTail.second.empty())
Operands.push_back(HexagonOperand::CreateToken(
- String.substr(HeadTail.first.size(), 1), Loc));
+ getContext(), String.substr(HeadTail.first.size(), 1), Loc));
String = HeadTail.second;
} while (!String.empty());
return false;
@@ -878,38 +910,43 @@ bool HexagonAsmParser::parseOperand(Oper
case Hexagon::P3:
if (previousEqual(Operands, 0, "if")) {
if (WarnMissingParenthesis)
- Warning (Begin, "Missing parenthesis around predicate register");
+ Warning(Begin, "Missing parenthesis around predicate register");
static char const *LParen = "(";
static char const *RParen = ")";
- Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
- Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
+ Operands.push_back(
+ HexagonOperand::CreateToken(getContext(), LParen, Begin));
+ Operands.push_back(
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));
const AsmToken &MaybeDotNew = Lexer.getTok();
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
MaybeDotNew.getString().equals_lower(".new"))
splitIdentifier(Operands);
- Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
+ Operands.push_back(
+ HexagonOperand::CreateToken(getContext(), RParen, Begin));
return false;
}
if (previousEqual(Operands, 0, "!") &&
previousEqual(Operands, 1, "if")) {
if (WarnMissingParenthesis)
- Warning (Begin, "Missing parenthesis around predicate register");
+ Warning(Begin, "Missing parenthesis around predicate register");
static char const *LParen = "(";
static char const *RParen = ")";
- Operands.insert(Operands.end () - 1,
- HexagonOperand::CreateToken(LParen, Begin));
- Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
+ Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
+ getContext(), LParen, Begin));
+ Operands.push_back(
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));
const AsmToken &MaybeDotNew = Lexer.getTok();
if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
MaybeDotNew.getString().equals_lower(".new"))
splitIdentifier(Operands);
- Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
+ Operands.push_back(
+ HexagonOperand::CreateToken(getContext(), RParen, Begin));
return false;
}
break;
}
- Operands.push_back(HexagonOperand::CreateReg(
- Register, Begin, End));
+ Operands.push_back(
+ HexagonOperand::CreateReg(getContext(), Register, Begin, End));
return false;
}
return splitIdentifier(Operands);
@@ -931,10 +968,9 @@ bool HexagonAsmParser::isLabel(AsmToken
return true;
if (!matchRegister(String.lower()))
return true;
- (void)Second;
assert(Second.is(AsmToken::Colon));
- StringRef Raw (String.data(), Third.getString().data() - String.data() +
- Third.getString().size());
+ StringRef Raw(String.data(), Third.getString().data() - String.data() +
+ Third.getString().size());
std::string Collapsed = Raw;
Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
StringRef Whole = Collapsed;
@@ -944,7 +980,8 @@ bool HexagonAsmParser::isLabel(AsmToken
return false;
}
-bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
+bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
+ SMLoc &Loc) {
if (!Contigious && ErrorNoncontigiousRegister) {
Error(Loc, "Register name is not contigious");
return true;
@@ -954,7 +991,8 @@ bool HexagonAsmParser::handleNoncontigio
return false;
}
-bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
+bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
MCAsmLexer &Lexer = getLexer();
StartLoc = getLexer().getLoc();
SmallVector<AsmToken, 5> Lookahead;
@@ -963,19 +1001,19 @@ bool HexagonAsmParser::ParseRegister(uns
bool NeededWorkaround = false;
while (Again) {
AsmToken const &Token = Lexer.getTok();
- RawString = StringRef(RawString.data(),
- Token.getString().data() - RawString.data () +
- Token.getString().size());
+ RawString = StringRef(RawString.data(), Token.getString().data() -
+ RawString.data() +
+ Token.getString().size());
Lookahead.push_back(Token);
Lexer.Lex();
bool Contigious = Lexer.getTok().getString().data() ==
Lookahead.back().getString().data() +
- Lookahead.back().getString().size();
+ Lookahead.back().getString().size();
bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
Lexer.is(AsmToken::Colon);
- bool Workaround = Lexer.is(AsmToken::Colon) ||
- Lookahead.back().is(AsmToken::Colon);
+ bool Workaround =
+ Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
Again = (Contigious && Type) || (Workaround && Type);
NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
}
@@ -1005,10 +1043,10 @@ bool HexagonAsmParser::ParseRegister(uns
std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
unsigned ColonReg = matchRegister(ColonSplit.first.lower());
if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
- Lexer.UnLex(Lookahead.back());
- Lookahead.pop_back();
- Lexer.UnLex(Lookahead.back());
- Lookahead.pop_back();
+ do {
+ Lexer.UnLex(Lookahead.back());
+ Lookahead.pop_back();
+ } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));
RegNo = ColonReg;
EndLoc = Lexer.getLoc();
if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
@@ -1036,19 +1074,18 @@ bool HexagonAsmParser::implicitExpressio
return false;
}
-bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
+bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
SmallVector<AsmToken, 4> Tokens;
MCAsmLexer &Lexer = getLexer();
bool Done = false;
- static char const * Comma = ",";
+ static char const *Comma = ",";
do {
- Tokens.emplace_back (Lexer.getTok());
+ Tokens.emplace_back(Lexer.getTok());
Lex();
- switch (Tokens.back().getKind())
- {
+ switch (Tokens.back().getKind()) {
case AsmToken::TokenKind::Hash:
- if (Tokens.size () > 1)
- if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
+ if (Tokens.size() > 1)
+ if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
Tokens.insert(Tokens.end() - 2,
AsmToken(AsmToken::TokenKind::Comma, Comma));
Done = true;
@@ -1067,7 +1104,8 @@ bool HexagonAsmParser::parseExpression(M
Lexer.UnLex(Tokens.back());
Tokens.pop_back();
}
- return getParser().parseExpression(Expr);
+ SMLoc Loc = Lexer.getLoc();
+ return getParser().parseExpression(Expr, Loc);
}
bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
@@ -1078,7 +1116,8 @@ bool HexagonAsmParser::parseExpressionOr
bool Error = parseExpression(Expr);
Expr = HexagonMCExpr::create(Expr, getContext());
if (!Error)
- Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
+ Operands.push_back(
+ HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
return Error;
}
return parseOperand(Operands);
@@ -1091,6 +1130,7 @@ bool HexagonAsmParser::parseInstruction(
while (true) {
AsmToken const &Token = Parser.getTok();
switch (Token.getKind()) {
+ case AsmToken::Eof:
case AsmToken::EndOfStatement: {
Lex();
return false;
@@ -1098,15 +1138,15 @@ bool HexagonAsmParser::parseInstruction(
case AsmToken::LCurly: {
if (!Operands.empty())
return true;
- Operands.push_back(
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+ Operands.push_back(HexagonOperand::CreateToken(
+ getContext(), Token.getString(), Token.getLoc()));
Lex();
return false;
}
case AsmToken::RCurly: {
if (Operands.empty()) {
- Operands.push_back(
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+ Operands.push_back(HexagonOperand::CreateToken(
+ getContext(), Token.getString(), Token.getLoc()));
Lex();
}
return false;
@@ -1122,9 +1162,9 @@ bool HexagonAsmParser::parseInstruction(
case AsmToken::LessEqual:
case AsmToken::LessLess: {
Operands.push_back(HexagonOperand::CreateToken(
- Token.getString().substr(0, 1), Token.getLoc()));
+ getContext(), Token.getString().substr(0, 1), Token.getLoc()));
Operands.push_back(HexagonOperand::CreateToken(
- Token.getString().substr(1, 1), Token.getLoc()));
+ getContext(), Token.getString().substr(1, 1), Token.getLoc()));
Lex();
continue;
}
@@ -1133,8 +1173,8 @@ bool HexagonAsmParser::parseInstruction(
bool ImplicitExpression = implicitExpressionLocation(Operands);
SMLoc ExprLoc = Lexer.getLoc();
if (!ImplicitExpression)
- Operands.push_back(
- HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
+ Operands.push_back(HexagonOperand::CreateToken(
+ getContext(), Token.getString(), Token.getLoc()));
Lex();
bool MustExtend = false;
bool HiOnly = false;
@@ -1171,16 +1211,15 @@ bool HexagonAsmParser::parseInstruction(
if (Expr->evaluateAsAbsolute(Value)) {
if (HiOnly)
Expr = MCBinaryExpr::createLShr(
- Expr, MCConstantExpr::create(16, Context), Context);
+ Expr, MCConstantExpr::create(16, Context), Context);
if (HiOnly || LoOnly)
- Expr = MCBinaryExpr::createAnd(Expr,
- MCConstantExpr::create(0xffff, Context),
- Context);
+ Expr = MCBinaryExpr::createAnd(
+ Expr, MCConstantExpr::create(0xffff, Context), Context);
} else {
MCValue Value;
if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
if (!Value.isAbsolute()) {
- switch(Value.getAccessVariant()) {
+ switch (Value.getAccessVariant()) {
case MCSymbolRefExpr::VariantKind::VK_TPREL:
case MCSymbolRefExpr::VariantKind::VK_DTPREL:
// Don't lazy extend these expression variants
@@ -1196,7 +1235,7 @@ bool HexagonAsmParser::parseInstruction(
HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
std::unique_ptr<HexagonOperand> Operand =
- HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
+ HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
Operands.push_back(std::move(Operand));
continue;
}
@@ -1209,15 +1248,14 @@ bool HexagonAsmParser::parseInstruction(
}
bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
- StringRef Name,
- AsmToken ID,
+ StringRef Name, AsmToken ID,
OperandVector &Operands) {
getLexer().UnLex(ID);
return parseInstruction(Operands);
}
-static MCInst makeCombineInst(int opCode, MCOperand &Rdd,
- MCOperand &MO1, MCOperand &MO2) {
+static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
+ MCOperand &MO2) {
MCInst TmpInst;
TmpInst.setOpcode(opCode);
TmpInst.addOperand(Rdd);
@@ -1286,6 +1324,13 @@ int HexagonAsmParser::processInstruction
bool is32bit = false; // used to distinguish between CONST32 and CONST64
switch (Inst.getOpcode()) {
default:
+ if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
+ SMDiagnostic Diag = getSourceManager().GetMessage(
+ IDLoc, SourceMgr::DK_Error,
+ "Found pseudo instruction with no expansion");
+ Diag.print("", errs());
+ report_fatal_error("Invalid pseudo instruction");
+ }
break;
case Hexagon::A2_iconst: {
@@ -1319,8 +1364,10 @@ int HexagonAsmParser::processInstruction
case Hexagon::C2_cmpgei: {
MCOperand &MO = Inst.getOperand(2);
- MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
- MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+ MO.setExpr(HexagonMCExpr::create(
+ MCBinaryExpr::createSub(MO.getExpr(),
+ MCConstantExpr::create(1, Context), Context),
+ Context));
Inst.setOpcode(Hexagon::C2_cmpgti);
break;
}
@@ -1341,8 +1388,10 @@ int HexagonAsmParser::processInstruction
TmpInst.addOperand(Rt);
Inst = TmpInst;
} else {
- MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
- MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+ MO.setExpr(HexagonMCExpr::create(
+ MCBinaryExpr::createSub(MO.getExpr(),
+ MCConstantExpr::create(1, Context), Context),
+ Context));
Inst.setOpcode(Hexagon::C2_cmpgtui);
}
break;
@@ -1509,7 +1558,7 @@ int HexagonAsmParser::processInstruction
TmpInst.addOperand(MO_0);
TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
- MCSymbolRefExpr::create(Sym, getContext()), getContext())));
+ MCSymbolRefExpr::create(Sym, getContext()), getContext())));
Inst = TmpInst;
}
}
@@ -1540,7 +1589,8 @@ int HexagonAsmParser::processInstruction
MCConstantExpr::create(s8, Context), Context))); // upper 32
auto Expr = HexagonMCExpr::create(
MCConstantExpr::create(Lo_32(Value), Context), Context);
- HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
+ HexagonMCInstrInfo::setMustExtend(
+ *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
} else {
@@ -1588,15 +1638,16 @@ int HexagonAsmParser::processInstruction
case Hexagon::S2_tableidxh_goodsyntax: {
MCInst TmpInst;
MCOperand &Rx = Inst.getOperand(0);
- MCOperand &_dst_ = Inst.getOperand(1);
MCOperand &Rs = Inst.getOperand(2);
MCOperand &Imm4 = Inst.getOperand(3);
MCOperand &Imm6 = Inst.getOperand(4);
- Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
- Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
+ Imm6.setExpr(HexagonMCExpr::create(
+ MCBinaryExpr::createSub(Imm6.getExpr(),
+ MCConstantExpr::create(1, Context), Context),
+ Context));
TmpInst.setOpcode(Hexagon::S2_tableidxh);
TmpInst.addOperand(Rx);
- TmpInst.addOperand(_dst_);
+ TmpInst.addOperand(Rx);
TmpInst.addOperand(Rs);
TmpInst.addOperand(Imm4);
TmpInst.addOperand(Imm6);
@@ -1607,15 +1658,16 @@ int HexagonAsmParser::processInstruction
case Hexagon::S2_tableidxw_goodsyntax: {
MCInst TmpInst;
MCOperand &Rx = Inst.getOperand(0);
- MCOperand &_dst_ = Inst.getOperand(1);
MCOperand &Rs = Inst.getOperand(2);
MCOperand &Imm4 = Inst.getOperand(3);
MCOperand &Imm6 = Inst.getOperand(4);
- Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
- Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context));
+ Imm6.setExpr(HexagonMCExpr::create(
+ MCBinaryExpr::createSub(Imm6.getExpr(),
+ MCConstantExpr::create(2, Context), Context),
+ Context));
TmpInst.setOpcode(Hexagon::S2_tableidxw);
TmpInst.addOperand(Rx);
- TmpInst.addOperand(_dst_);
+ TmpInst.addOperand(Rx);
TmpInst.addOperand(Rs);
TmpInst.addOperand(Imm4);
TmpInst.addOperand(Imm6);
@@ -1626,15 +1678,16 @@ int HexagonAsmParser::processInstruction
case Hexagon::S2_tableidxd_goodsyntax: {
MCInst TmpInst;
MCOperand &Rx = Inst.getOperand(0);
- MCOperand &_dst_ = Inst.getOperand(1);
MCOperand &Rs = Inst.getOperand(2);
MCOperand &Imm4 = Inst.getOperand(3);
MCOperand &Imm6 = Inst.getOperand(4);
- Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
- Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context));
+ Imm6.setExpr(HexagonMCExpr::create(
+ MCBinaryExpr::createSub(Imm6.getExpr(),
+ MCConstantExpr::create(3, Context), Context),
+ Context));
TmpInst.setOpcode(Hexagon::S2_tableidxd);
TmpInst.addOperand(Rx);
- TmpInst.addOperand(_dst_);
+ TmpInst.addOperand(Rx);
TmpInst.addOperand(Rs);
TmpInst.addOperand(Imm4);
TmpInst.addOperand(Imm6);
@@ -1655,21 +1708,15 @@ int HexagonAsmParser::processInstruction
bool Absolute = Expr.evaluateAsAbsolute(Value);
assert(Absolute);
(void)Absolute;
- if (!HexagonMCInstrInfo::mustExtend(Expr)) {
- if (Value < 0 && Value > -256) {
- Imm.setExpr(HexagonMCExpr::create(
- MCConstantExpr::create(Value * -1, Context), Context));
- TmpInst.setOpcode(Hexagon::M2_mpysin);
- } else if (Value < 256 && Value >= 0)
- TmpInst.setOpcode(Hexagon::M2_mpysip);
- else
- return Match_InvalidOperand;
- } else {
- if (Value >= 0)
- TmpInst.setOpcode(Hexagon::M2_mpysip);
- else
- return Match_InvalidOperand;
- }
+ if (!HexagonMCInstrInfo::mustExtend(Expr) &&
+ ((Value <= -256) || Value >= 256))
+ return Match_InvalidOperand;
+ if (Value < 0 && Value > -256) {
+ Imm.setExpr(HexagonMCExpr::create(
+ MCConstantExpr::create(Value * -1, Context), Context));
+ TmpInst.setOpcode(Hexagon::M2_mpysin);
+ } else
+ TmpInst.setOpcode(Hexagon::M2_mpysip);
TmpInst.addOperand(Rd);
TmpInst.addOperand(Rs);
TmpInst.addOperand(Imm);
@@ -1952,7 +1999,8 @@ int HexagonAsmParser::processInstruction
break;
case Hexagon::A2_zxtb: {
Inst.setOpcode(Hexagon::A2_andir);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, Context)));
+ Inst.addOperand(
+ MCOperand::createExpr(MCConstantExpr::create(255, Context)));
break;
}
} // switch
Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Mon Dec 11 10:57:54 2017
@@ -27,6 +27,7 @@ add_llvm_target(HexagonCodeGen
HexagonExpandCondsets.cpp
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp
+ HexagonGatherPacketize.cpp
HexagonGenExtract.cpp
HexagonGenInsert.cpp
HexagonGenMux.cpp
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Mon Dec 11 10:57:54 2017
@@ -45,10 +45,12 @@ class HexagonDisassembler : public MCDis
public:
std::unique_ptr<MCInstrInfo const> const MCII;
std::unique_ptr<MCInst *> CurrentBundle;
+ mutable MCInst const *CurrentExtender;
HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
MCInstrInfo const *MCII)
- : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}
+ : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
+ CurrentExtender(nullptr) {}
DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -58,40 +60,38 @@ public:
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &VStream,
raw_ostream &CStream) const override;
- void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
+ void remapInstruction(MCInst &Instr) const;
};
-} // end anonymous namespace
-
-static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI,
+static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
int64_t Value) {
- MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
- MCB, HexagonMCInstrInfo::bundleSize(MCB));
- if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
+ MCInstrInfo MCII = *Disassembler.MCII;
+ if (!Disassembler.CurrentExtender ||
+ MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
return Value;
unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
int64_t Bits;
- bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);
- assert(Success); (void)Success;
- uint32_t Upper26 = static_cast<uint32_t>(Bits);
- uint32_t Operand = Upper26 | Lower6;
+ bool Success =
+ Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
+ Bits);
+ assert(Success);
+ (void)Success;
+ uint64_t Upper26 = static_cast<uint64_t>(Bits);
+ uint64_t Operand = Upper26 | Lower6;
return Operand;
}
-
static HexagonDisassembler const &disassembler(void const *Decoder) {
return *static_cast<HexagonDisassembler const *>(Decoder);
}
-
template <size_t T>
static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
HexagonDisassembler const &Disassembler = disassembler(Decoder);
- int64_t FullValue =
- fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
- SignExtend64<T>(tmp));
+ int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
int64_t Extended = SignExtend64<32>(FullValue);
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
}
+}
// Forward declare these because the auto-generated code will reference them.
// Definitions are further down.
@@ -107,8 +107,8 @@ static DecodeStatus DecodeIntRegsLow8Reg
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
+ uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
@@ -116,14 +116,14 @@ static DecodeStatus
DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
+ uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder);
+ uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
@@ -141,62 +141,7 @@ static DecodeStatus s32_0ImmDecoder(MCIn
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
-static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<4>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<14>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<8>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<7>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<12>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<3>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<13>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<6>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<9>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<5>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
- const void *Decoder) {
- signedDecoder<6>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-
+#include "HexagonDepDecoders.h"
#include "HexagonGenDisassemblerTables.inc"
static MCDisassembler *createHexagonDisassembler(const Target &T,
@@ -215,12 +160,15 @@ DecodeStatus HexagonDisassembler::getIns
uint64_t Address,
raw_ostream &os,
raw_ostream &cs) const {
+ (void)&s10_0ImmDecoder;
+ (void)&s10_6ImmDecoder;
DecodeStatus Result = DecodeStatus::Success;
bool Complete = false;
Size = 0;
*CurrentBundle = &MI;
- MI = HexagonMCInstrInfo::createBundle();
+ MI.setOpcode(Hexagon::BUNDLE);
+ MI.addOperand(MCOperand::createImm(0));
while (Result == Success && !Complete) {
if (Bytes.size() < HEXAGON_INSTR_SIZE)
return MCDisassembler::Fail;
@@ -238,9 +186,89 @@ DecodeStatus HexagonDisassembler::getIns
*getContext().getRegisterInfo(), false);
if (!Checker.check())
return MCDisassembler::Fail;
+ remapInstruction(MI);
return MCDisassembler::Success;
}
+void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
+ for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
+ auto &MI = const_cast<MCInst &>(*I.getInst());
+ switch (MI.getOpcode()) {
+ case Hexagon::S2_allocframe:
+ if (MI.getOperand(0).getReg() == Hexagon::R29) {
+ MI.setOpcode(Hexagon::S6_allocframe_to_raw);
+ MI.erase(MI.begin () + 1);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L2_deallocframe:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(1).getReg() == Hexagon::R30) {
+ MI.setOpcode(L6_deallocframe_map_to_raw);
+ MI.erase(MI.begin () + 1);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(1).getReg() == Hexagon::R30) {
+ MI.setOpcode(L6_return_map_to_raw);
+ MI.erase(MI.begin () + 1);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_t:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_t);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_f:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_f);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_tnew_pt:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_tnew_pt);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_fnew_pt:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_fnew_pt);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_tnew_pnt:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ case Hexagon::L4_return_fnew_pnt:
+ if (MI.getOperand(0).getReg() == Hexagon::D15 &&
+ MI.getOperand(2).getReg() == Hexagon::R30) {
+ MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
+ MI.erase(MI.begin () + 2);
+ MI.erase(MI.begin ());
+ }
+ break;
+ }
+ }
+}
+
static void adjustDuplex(MCInst &MI, MCContext &Context) {
switch (MI.getOpcode()) {
case Hexagon::SA1_setin1:
@@ -274,7 +302,7 @@ DecodeStatus HexagonDisassembler::getSin
return DecodeStatus::Fail;
}
- MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
+ CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
MCB, HexagonMCInstrInfo::bundleSize(MCB));
DecodeStatus Result = DecodeStatus::Fail;
@@ -350,8 +378,12 @@ DecodeStatus HexagonDisassembler::getSin
MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
MCInst *MILow = new (getContext()) MCInst;
MCInst *MIHigh = new (getContext()) MCInst;
+ auto TmpExtender = CurrentExtender;
+ CurrentExtender =
+ nullptr; // constant extenders in duplex must always be in slot 1
Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
this, STI);
+ CurrentExtender = TmpExtender;
if (Result != DecodeStatus::Success)
return DecodeStatus::Fail;
adjustDuplex(*MILow, getContext());
@@ -370,7 +402,7 @@ DecodeStatus HexagonDisassembler::getSin
HexagonII::INST_PARSE_PACKET_END)
Complete = true;
- if (Extender != nullptr)
+ if (CurrentExtender != nullptr)
Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
Address, this, STI);
@@ -429,25 +461,29 @@ DecodeStatus HexagonDisassembler::getSin
unsigned Lookback = (Register & 0x6) >> 1;
unsigned Offset = 1;
bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
+ bool PrevVector = false;
auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
auto i = Instructions.end() - 1;
for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
if (i == n)
// Couldn't find producer
return MCDisassembler::Fail;
- if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst()))
+ bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
+ if (Vector && !CurrentVector)
// Skip scalars when calculating distances for vectors
++Lookback;
- if (HexagonMCInstrInfo::isImmext(*i->getInst()))
+ if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
++Lookback;
+ PrevVector = CurrentVector;
if (Offset == Lookback)
break;
}
auto const &Inst = *i->getInst();
bool SubregBit = (Register & 0x1) != 0;
- if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
+ if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
// If subreg bit is set we're selecting the second produced newvalue
- unsigned Producer =
+ unsigned Producer = SubregBit ?
+ HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
assert(Producer != Hexagon::NoRegister);
MCO.setReg(Producer);
@@ -466,7 +502,7 @@ DecodeStatus HexagonDisassembler::getSin
return MCDisassembler::Fail;
}
- if (Extender != nullptr) {
+ if (CurrentExtender != nullptr) {
MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
? *MI.getOperand(1).getInst()
: MI;
@@ -666,8 +702,7 @@ static DecodeStatus unsignedImmDecoder(M
uint64_t /*Address*/,
const void *Decoder) {
HexagonDisassembler const &Disassembler = disassembler(Decoder);
- int64_t FullValue =
- fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp);
+ int64_t FullValue = fullValue(Disassembler, MI, tmp);
assert(FullValue >= 0 && "Negative in unsigned decoder");
HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
return MCDisassembler::Success;
@@ -690,10 +725,8 @@ static DecodeStatus brtargetDecoder(MCIn
// r13_2 is not extendable, so if there are no extent bits, it's r13_2
if (Bits == 0)
Bits = 15;
- uint32_t FullValue =
- fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
- SignExtend64(tmp, Bits));
- int64_t Extended = SignExtend64<32>(FullValue) + Address;
+ uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
+ uint32_t Extended = FullValue + Address;
if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
return MCDisassembler::Success;
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Mon Dec 11 10:57:54 2017
@@ -25,33 +25,36 @@ include "llvm/Target/Target.td"
include "HexagonDepArch.td"
// Hexagon ISA Extensions
-def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
+def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
"Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
+def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
+ "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
+ [ExtensionHVX]>;
def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
"Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
- [ExtensionHVXV60]>;
-def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
- "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
- [ExtensionHVXV60,
- ExtensionHVXV62]>;
+ [ExtensionHVX,ExtensionHVXV60]>;
+def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
+ "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
+ [ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
def ExtensionHVX64B
: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
- "Hexagon HVX 64B instructions",
- [ExtensionHVXV60, ExtensionHVXV62]>;
+ "Hexagon HVX 64B instructions", [ExtensionHVX]>;
def ExtensionHVX128B
: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
- "Hexagon HVX 128B instructions",
- [ExtensionHVXV60, ExtensionHVXV62]>;
+ "Hexagon HVX 128B instructions", [ExtensionHVX]>;
// This is an alias to ExtensionHVX128B to accept the hvx-double as
// an acceptable subtarget feature.
def ExtensionHVXDbl
: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
- "Hexagon HVX 128B instructions",
- [ExtensionHVXV60, ExtensionHVXV62]>;
+ "Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Use constant-extended calls">;
+def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
+ "Supports mem_noshuf feature">;
+def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
+ "Enable generation of duplex instruction">;
//===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions.
@@ -69,6 +72,8 @@ def UseHVXV60 : Predicate<"HST-
AssemblerPredicate<"ExtensionHVXV60">;
def UseHVXV62 : Predicate<"HST->useHVXOps()">,
AssemblerPredicate<"ExtensionHVXV62">;
+def UseHVXV65 : Predicate<"HST->useHVXOps()">,
+ AssemblerPredicate<"ExtensionHVXV65">;
def Hvx64 : HwMode<"+hvx-length64b">;
def Hvx64old : HwMode<"-hvx-double">;
@@ -80,21 +85,22 @@ def Hvx128old : HwMode<"+hvx-double">;
//===----------------------------------------------------------------------===//
class ImmRegShl;
+// ImmRegRel - Filter class used to relate instructions having reg-reg form
+// with their reg-imm counterparts.
+class ImmRegRel;
// PredRel - Filter class used to relate non-predicated instructions with their
// predicated forms.
class PredRel;
// PredNewRel - Filter class used to relate predicated instructions with their
// predicate-new forms.
class PredNewRel: PredRel;
-// ImmRegRel - Filter class used to relate instructions having reg-reg form
-// with their reg-imm counterparts.
-class ImmRegRel;
// NewValueRel - Filter class used to relate regular store instructions with
// their new-value store form.
class NewValueRel: PredNewRel;
// NewValueRel - Filter class used to relate load/store instructions having
// different addressing modes with each other.
class AddrModeRel: NewValueRel;
+class PostInc_BaseImm;
class IntrinsicsRel;
//===----------------------------------------------------------------------===//
@@ -220,6 +226,22 @@ def changeAddrMode_rr_io: InstrMapping {
let ValueCols = [["BaseImmOffset"]];
}
+def changeAddrMode_pi_io: InstrMapping {
+ let FilterClass = "PostInc_BaseImm";
+ let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+ let ColFields = ["addrMode"];
+ let KeyCol = ["PostInc"];
+ let ValueCols = [["BaseImmOffset"]];
+}
+
+def changeAddrMode_io_pi: InstrMapping {
+ let FilterClass = "PostInc_BaseImm";
+ let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+ let ColFields = ["addrMode"];
+ let KeyCol = ["BaseImmOffset"];
+ let ValueCols = [["PostInc"]];
+}
+
def changeAddrMode_rr_ur: InstrMapping {
let FilterClass = "ImmRegShl";
let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
@@ -268,7 +290,7 @@ def getRealHWInstr : InstrMapping {
let ValueCols = [["Pseudo"], ["Real"]];
}
//===----------------------------------------------------------------------===//
-// Register File, Calling Conv, Instruction Descriptions
+// Register File, Instruction Descriptions
//===----------------------------------------------------------------------===//
include "HexagonSchedule.td"
include "HexagonRegisterInfo.td"
@@ -280,9 +302,11 @@ include "HexagonDepInstrFormats.td"
include "HexagonDepInstrInfo.td"
include "HexagonPseudo.td"
include "HexagonPatterns.td"
+include "HexagonPatternsV65.td"
include "HexagonDepMappings.td"
include "HexagonIntrinsics.td"
include "HexagonMapAsm2IntrinV62.gen.td"
+include "HexagonMapAsm2IntrinV65.gen.td"
def HexagonInstrInfo : InstrInfo;
@@ -295,15 +319,18 @@ class Proc<string Name, SchedMachineMode
: ProcessorModel<Name, Model, Features>;
def : Proc<"hexagonv4", HexagonModelV4,
- [ArchV4]>;
+ [ArchV4, FeatureDuplex]>;
def : Proc<"hexagonv5", HexagonModelV4,
- [ArchV4, ArchV5]>;
+ [ArchV4, ArchV5, FeatureDuplex]>;
def : Proc<"hexagonv55", HexagonModelV55,
- [ArchV4, ArchV5, ArchV55]>;
+ [ArchV4, ArchV5, ArchV55, FeatureDuplex]>;
def : Proc<"hexagonv60", HexagonModelV60,
- [ArchV4, ArchV5, ArchV55, ArchV60]>;
+ [ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>;
def : Proc<"hexagonv62", HexagonModelV62,
- [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>;
+ [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>;
+def : Proc<"hexagonv65", HexagonModelV65,
+ [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
+ FeatureMemNoShuf, FeatureDuplex]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
@@ -317,11 +344,17 @@ def HexagonAsmParser : AsmParser {
def HexagonAsmParserVariant : AsmParserVariant {
int Variant = 0;
string TokenizingCharacters = "#()=:.<>!+*-|^&";
+ string BreakCharacters = "";
+}
+
+def HexagonAsmWriter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
}
def Hexagon : Target {
- // Pull in Instruction Info:
let InstructionSet = HexagonInstrInfo;
let AssemblyParsers = [HexagonAsmParser];
let AssemblyParserVariants = [HexagonAsmParserVariant];
+ let AssemblyWriters = [HexagonAsmWriter];
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Mon Dec 11 10:57:54 2017
@@ -615,7 +615,18 @@ void HexagonAsmPrinter::HexagonProcessIn
MappedInst = TmpInst;
return;
}
-
+ case Hexagon::V6_vdd0: {
+ MCInst TmpInst;
+ assert (Inst.getOperand(0).isReg() &&
+ "Expected register and none was found");
+
+ TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(0));
+ MappedInst = TmpInst;
+ return;
+ }
case Hexagon::V6_vL32Ub_pi:
case Hexagon::V6_vL32b_cur_pi:
case Hexagon::V6_vL32b_nt_cur_pi:
@@ -715,13 +726,25 @@ void HexagonAsmPrinter::HexagonProcessIn
case Hexagon::V6_vS32b_qpred_ai:
MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
return;
+
+ // V65+
+ case Hexagon::V6_vS32b_srls_ai:
+ MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vS32b_srls_pi:
+ MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
+ return;
+
}
}
/// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
/// the current output stream.
void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
- MCInst MCB = HexagonMCInstrInfo::createBundle();
+ MCInst MCB;
+ MCB.setOpcode(Hexagon::BUNDLE);
+ MCB.addOperand(MCOperand::createImm(0));
const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
if (MI->isBundle()) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepArch.h -------------------------------------------------===//
+//===- HexagonDepArch.h ---------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,12 +6,16 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+
#ifndef HEXAGON_DEP_ARCH_H
#define HEXAGON_DEP_ARCH_H
namespace llvm {
namespace Hexagon {
-enum class ArchEnum { V4, V5, V55, V60, V62 };
+enum class ArchEnum { V4,V5,V55,V60,V62,V65 };
} // namespace Hexagon
-} // namespace llvm
+} // namespace llvm;
#endif // HEXAGON_DEP_ARCH_H
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepArch.td ------------------------------------------------===//
+//===- HexagonDepArch.td --------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,7 +6,12 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">;
+def HasV65T : Predicate<"HST->hasV65TOps()">, AssemblerPredicate<"ArchV65">;
def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">;
def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">;
def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">;
Added: llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h?rev=320404&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h Mon Dec 11 10:57:54 2017
@@ -0,0 +1,78 @@
+//===- HexagonDepDecoders.h -----------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
+
+
+static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<4>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<14>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s10_6ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<16>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<8>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<7>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<12>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<3>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<13>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<6>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<9>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<5>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<6>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
+static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<10>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepIICHVX.td Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepIICHVX.td ----------------------------------------------===//
+//===- HexagonDepIICHVX.td ------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,11 +6,15 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
def tc_0317c6ca : InstrItinClass;
def tc_1b93bdc6 : InstrItinClass;
def tc_2171ebae : InstrItinClass;
def tc_28978789 : InstrItinClass;
+def tc_29841470 : InstrItinClass;
def tc_316c637c : InstrItinClass;
def tc_354299ad : InstrItinClass;
def tc_35e92f8e : InstrItinClass;
@@ -20,39 +24,49 @@ def tc_41f4b64e : InstrItinClass;
def tc_41f99e1c : InstrItinClass;
def tc_45453b98 : InstrItinClass;
def tc_4e2a5159 : InstrItinClass;
+def tc_4f190ba3 : InstrItinClass;
def tc_4fd8566e : InstrItinClass;
def tc_51cd3aab : InstrItinClass;
def tc_5a9fc4ec : InstrItinClass;
+def tc_5c03dc63 : InstrItinClass;
def tc_5c120602 : InstrItinClass;
def tc_5cbf490b : InstrItinClass;
+def tc_63e3d94c : InstrItinClass;
def tc_644584f8 : InstrItinClass;
+def tc_66bb62ea : InstrItinClass;
def tc_69b6dd20 : InstrItinClass;
def tc_6b78cf13 : InstrItinClass;
def tc_6fd9ad30 : InstrItinClass;
def tc_71337255 : InstrItinClass;
def tc_72ad7b54 : InstrItinClass;
+def tc_7474003e : InstrItinClass;
def tc_77a4c701 : InstrItinClass;
def tc_7c3f55c4 : InstrItinClass;
def tc_7e9f581b : InstrItinClass;
def tc_7fa82b08 : InstrItinClass;
def tc_7fa8b40f : InstrItinClass;
def tc_85d237e3 : InstrItinClass;
+def tc_8a6eb39a : InstrItinClass;
def tc_8b6a873f : InstrItinClass;
def tc_908a4c8c : InstrItinClass;
def tc_9311da3f : InstrItinClass;
+def tc_94f43c04 : InstrItinClass;
def tc_9777e6bf : InstrItinClass;
def tc_97c165b9 : InstrItinClass;
+def tc_98733e9d : InstrItinClass;
def tc_99093773 : InstrItinClass;
def tc_9b9642a1 : InstrItinClass;
def tc_9c267309 : InstrItinClass;
def tc_a3127e12 : InstrItinClass;
def tc_a4c9df3b : InstrItinClass;
+def tc_a807365d : InstrItinClass;
def tc_aedb9f9e : InstrItinClass;
def tc_b06ab583 : InstrItinClass;
def tc_b712833a : InstrItinClass;
def tc_b77635b4 : InstrItinClass;
def tc_bbaf280e : InstrItinClass;
def tc_bf142ae2 : InstrItinClass;
+def tc_bfe309d5 : InstrItinClass;
def tc_c00bf9c9 : InstrItinClass;
def tc_c4b515c5 : InstrItinClass;
def tc_cbf6d1dc : InstrItinClass;
@@ -65,14 +79,18 @@ def tc_d7bea0ec : InstrItinClass;
def tc_d98f4d63 : InstrItinClass;
def tc_da979fb3 : InstrItinClass;
def tc_db5b9e2f : InstrItinClass;
+def tc_df54ad52 : InstrItinClass;
def tc_e172d86a : InstrItinClass;
def tc_e231aa4f : InstrItinClass;
def tc_e3748cdf : InstrItinClass;
def tc_e5053c8f : InstrItinClass;
def tc_e6299d16 : InstrItinClass;
def tc_eb669007 : InstrItinClass;
+def tc_ec58f88a : InstrItinClass;
def tc_eda67dcd : InstrItinClass;
+def tc_ee927c0e : InstrItinClass;
def tc_f3fc3f83 : InstrItinClass;
+def tc_fa99dc24 : InstrItinClass;
class DepHVXItinV55 {
list<InstrItinData> DepHVXItinV55_list = [
@@ -97,6 +115,11 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_ALL]>], [3, 2],
[HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_29841470, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -146,6 +169,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
@@ -163,6 +192,11 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -174,11 +208,23 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -206,6 +252,11 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -239,6 +290,11 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+ [HVX_FWD]>,
+
InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -254,6 +310,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -264,6 +326,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -291,6 +359,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -323,6 +397,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -386,6 +466,12 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -418,15 +504,32 @@ class DepHVXItinV55 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
- [HVX_FWD, HVX_FWD, HVX_FWD]>
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>
];
}
@@ -453,6 +556,11 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_ALL]>], [3, 2],
[HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_29841470, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -502,6 +610,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
@@ -519,6 +633,11 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -530,11 +649,23 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -562,6 +693,11 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -595,6 +731,11 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+ [HVX_FWD]>,
+
InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -610,6 +751,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -620,6 +767,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -647,6 +800,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -679,6 +838,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -742,6 +907,12 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -774,15 +945,32 @@ class DepHVXItinV60 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
- [HVX_FWD, HVX_FWD, HVX_FWD]>
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>
];
}
@@ -809,6 +997,11 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_ALL]>], [3, 2],
[HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_29841470, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
@@ -858,6 +1051,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [SLOT1], 0>,
@@ -875,6 +1074,11 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
@@ -886,11 +1090,23 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
[HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
@@ -918,6 +1134,11 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
[InstrStage<1, [SLOT0, SLOT1], 0>,
InstrStage<1, [CVI_LD]>], [9, 1, 2],
@@ -951,6 +1172,11 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+ [HVX_FWD]>,
+
InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
@@ -966,6 +1192,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
@@ -976,6 +1208,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -1003,6 +1241,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_ST], 0>,
@@ -1035,6 +1279,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
[HVX_FWD, HVX_FWD, Hex_FWD]>,
+ InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
@@ -1098,6 +1348,12 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+ InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
@@ -1130,14 +1386,472 @@ class DepHVXItinV62 {
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
[InstrStage<1, [SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
[HVX_FWD, HVX_FWD, HVX_FWD]>,
+ InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
- [HVX_FWD, HVX_FWD, HVX_FWD]>
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>
+ ];
+}
+
+class DepHVXItinV65 {
+ list<InstrItinData> DepHVXItinV65_list = [
+ InstrItinData <tc_0317c6ca, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_1b93bdc6, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2, 5],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_2171ebae, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_28978789, /*SLOT0123,4SLOT*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ALL]>], [3, 2],
+ [HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_29841470, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_354299ad, /*SLOT0,NOSLOT1,STORE,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_XLANE]>], [1, 2, 5],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_35e92f8e, /*SLOT0,NOSLOT1,LOAD,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_38208312, /*SLOT01,LOAD*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4105d6b5, /*SLOT0123,VP*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 2],
+ [HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41f4b64e, /*SLOT0123,VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_SHIFT]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41f99e1c, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_45453b98, /*SLOT0123,VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_4e2a5159, /*SLOT0123,VP_VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_51cd3aab, /*SLOT01,LOAD*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD]>], [9, 2, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5a9fc4ec, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5cbf490b, /*SLOT01,LOAD,VA*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
+ [HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_69b6dd20, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6b78cf13, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2],
+ [HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6fd9ad30, /*SLOT0,NOSLOT1,STORE,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_71337255, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7],
+ [HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_72ad7b54, /*SLOT0123,VP_VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD]>], [9, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7c3f55c4, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7e9f581b, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7fa82b08, /*SLOT0,NOSLOT1,STORE,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_7fa8b40f, /*SLOT0123,VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_85d237e3, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
+ [HVX_FWD]>,
+
+ InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_908a4c8c, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_9311da3f, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
+ [Hex_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_97c165b9, /*SLOT0123,VA_DV*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7],
+ [Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_9b9642a1, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_9c267309, /*SLOT01,LOAD*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD]>], [9, 3, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a3127e12, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_a4c9df3b, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_b06ab583, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
+ [HVX_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_b712833a, /*SLOT01,LOAD,VA*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b77635b4, /*SLOT0123,4SLOT*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ALL]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_bbaf280e, /*SLOT0123,VA*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_bf142ae2, /*SLOT0123,VP*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/
+ [InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c4b515c5, /*SLOT0123,VP*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cbf6d1dc, /*SLOT0123,VP_VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cedf314b, /*SLOT0123,4SLOT*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ALL]>], [3],
+ [HVX_FWD]>,
+
+ InstrItinData <tc_d2cb81ea, /*SLOT0123,VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_SHIFT]>], [9, 5],
+ [HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_d5090f3e, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_d642eff3, /*SLOT0,NOSLOT1,STORE,VP*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_d725e5b0, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d7bea0ec, /*SLOT0123,VP_VS*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLSHF]>], [9, 5],
+ [HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_d98f4d63, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_da979fb3, /*SLOT01,LOAD,VA*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_db5b9e2f, /*SLOT0,STORE*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
+ [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
+ [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_e231aa4f, /*SLOT23,VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e3748cdf, /*SLOT0,STORE,VA*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_e5053c8f, /*SLOT0123,4SLOT*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ALL]>], [],
+ []>,
+
+ InstrItinData <tc_e6299d16, /*SLOT0123,VP*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 5],
+ [HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_eb669007, /*SLOT01,LOAD,VA*/
+ [InstrStage<1, [SLOT0, SLOT1], 0>,
+ InstrStage<1, [CVI_LD], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
+ [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
+ [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
+ InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
+ [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
+ [HVX_FWD, HVX_FWD, HVX_FWD]>,
+
+ InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
+ [HVX_FWD, HVX_FWD, Hex_FWD]>
];
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepIICScalar.td Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepIICScalar.td -------------------------------------------===//
+//===- HexagonDepIICScalar.td ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,2499 +6,4185 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
-def tc_049dfb74 : InstrItinClass;
-def tc_0767081f : InstrItinClass;
-def tc_07ac815d : InstrItinClass;
-def tc_090485bb : InstrItinClass;
-def tc_09c86199 : InstrItinClass;
-def tc_09faec3b : InstrItinClass;
-def tc_0cb867f2 : InstrItinClass;
-def tc_1000eb10 : InstrItinClass;
-def tc_128719e8 : InstrItinClass;
-def tc_136c4786 : InstrItinClass;
-def tc_14da557c : InstrItinClass;
-def tc_1b6011fb : InstrItinClass;
-def tc_1b834fe7 : InstrItinClass;
-def tc_1e062b18 : InstrItinClass;
-def tc_1e69aa99 : InstrItinClass;
-def tc_1f9668cc : InstrItinClass;
-def tc_1fe8323c : InstrItinClass;
-def tc_20a8e109 : InstrItinClass;
-def tc_210b2456 : InstrItinClass;
-def tc_251c87b2 : InstrItinClass;
-def tc_261d9b78 : InstrItinClass;
-def tc_28d296df : InstrItinClass;
-def tc_29c14515 : InstrItinClass;
-def tc_2aaab1e0 : InstrItinClass;
-def tc_2c8fe5ae : InstrItinClass;
-def tc_2d1e6f5c : InstrItinClass;
-def tc_2e55aa16 : InstrItinClass;
-def tc_30665cb0 : InstrItinClass;
-def tc_336e698c : InstrItinClass;
-def tc_34e882a4 : InstrItinClass;
-def tc_35fb9d13 : InstrItinClass;
-def tc_37326008 : InstrItinClass;
-def tc_3993c58b : InstrItinClass;
-def tc_3b4892c6 : InstrItinClass;
-def tc_3bea1824 : InstrItinClass;
-def tc_3c10f809 : InstrItinClass;
-def tc_3d905451 : InstrItinClass;
-def tc_3e61d314 : InstrItinClass;
-def tc_3eab77bd : InstrItinClass;
-def tc_43068634 : InstrItinClass;
-def tc_45631a8d : InstrItinClass;
-def tc_47ab9233 : InstrItinClass;
-def tc_47f0b7ad : InstrItinClass;
-def tc_485bb57c : InstrItinClass;
-def tc_4997da4a : InstrItinClass;
-def tc_511f28f6 : InstrItinClass;
-def tc_537e2013 : InstrItinClass;
-def tc_53ee6546 : InstrItinClass;
-def tc_548f402d : InstrItinClass;
-def tc_5625c6c1 : InstrItinClass;
-def tc_580a779c : InstrItinClass;
-def tc_583510c7 : InstrItinClass;
-def tc_5d806107 : InstrItinClass;
-def tc_5fa2857c : InstrItinClass;
-def tc_5fe9fcd0 : InstrItinClass;
-def tc_6264c5e0 : InstrItinClass;
-def tc_639d93ee : InstrItinClass;
-def tc_63cd9d2d : InstrItinClass;
-def tc_65dc7cc4 : InstrItinClass;
-def tc_69bb508b : InstrItinClass;
-def tc_6c52d277 : InstrItinClass;
-def tc_6c576d46 : InstrItinClass;
-def tc_70cabf66 : InstrItinClass;
-def tc_7639d4b0 : InstrItinClass;
-def tc_7675c0e9 : InstrItinClass;
-def tc_76c4c5ef : InstrItinClass;
-def tc_77781686 : InstrItinClass;
-def tc_78b3c689 : InstrItinClass;
-def tc_7986ba30 : InstrItinClass;
-def tc_7bc567a7 : InstrItinClass;
-def tc_7c2dcd4d : InstrItinClass;
-def tc_7ca2ea10 : InstrItinClass;
-def tc_7d01cbdc : InstrItinClass;
-def tc_7d9a56cd : InstrItinClass;
-def tc_81a23d44 : InstrItinClass;
-def tc_821c4233 : InstrItinClass;
-def tc_82f0f122 : InstrItinClass;
-def tc_84630363 : InstrItinClass;
-def tc_86442910 : InstrItinClass;
-def tc_87601822 : InstrItinClass;
-def tc_88fa2da6 : InstrItinClass;
-def tc_8c8041e6 : InstrItinClass;
-def tc_8cb685d9 : InstrItinClass;
-def tc_8def9c57 : InstrItinClass;
-def tc_8f0a6bad : InstrItinClass;
-def tc_8fab9ac3 : InstrItinClass;
-def tc_92d1833c : InstrItinClass;
-def tc_94e6ffd9 : InstrItinClass;
-def tc_95c54f8b : InstrItinClass;
-def tc_9a13af9d : InstrItinClass;
-def tc_9b73d261 : InstrItinClass;
-def tc_9c18c9a5 : InstrItinClass;
-def tc_9c68db63 : InstrItinClass;
-def tc_9ce7a5ab : InstrItinClass;
-def tc_9da3628f : InstrItinClass;
-def tc_9dafb7d3 : InstrItinClass;
-def tc_9df8b0dc : InstrItinClass;
-def tc_9e86015f : InstrItinClass;
-def tc_9f518242 : InstrItinClass;
-def tc_a12a5971 : InstrItinClass;
-def tc_a1fb80e1 : InstrItinClass;
-def tc_a333d2a9 : InstrItinClass;
-def tc_a4567c39 : InstrItinClass;
-def tc_a87879e8 : InstrItinClass;
-def tc_a9c993d9 : InstrItinClass;
-def tc_aad55963 : InstrItinClass;
-def tc_ab1b5e74 : InstrItinClass;
-def tc_ae0722f7 : InstrItinClass;
-def tc_ae2c2dc2 : InstrItinClass;
-def tc_ae762521 : InstrItinClass;
-def tc_b08b653e : InstrItinClass;
-def tc_b08be45e : InstrItinClass;
-def tc_b0f50e3c : InstrItinClass;
-def tc_b189ad4c : InstrItinClass;
-def tc_b324366f : InstrItinClass;
-def tc_b5bfaa60 : InstrItinClass;
-def tc_b5f5a094 : InstrItinClass;
-def tc_b86c7e8b : InstrItinClass;
-def tc_baccf077 : InstrItinClass;
-def tc_bc5561d8 : InstrItinClass;
-def tc_bcf0e36e : InstrItinClass;
-def tc_bd16579e : InstrItinClass;
-def tc_be995eaf : InstrItinClass;
-def tc_bf6fa601 : InstrItinClass;
-def tc_c0cd91a8 : InstrItinClass;
-def tc_c14739d5 : InstrItinClass;
-def tc_c1dbc916 : InstrItinClass;
-def tc_c58f771a : InstrItinClass;
-def tc_c85212ca : InstrItinClass;
-def tc_c8f9a6f6 : InstrItinClass;
-def tc_ca280e8b : InstrItinClass;
-def tc_cbe45117 : InstrItinClass;
-def tc_cd321066 : InstrItinClass;
-def tc_d108a090 : InstrItinClass;
-def tc_d1b5a4b6 : InstrItinClass;
-def tc_d2609065 : InstrItinClass;
-def tc_d267fa19 : InstrItinClass;
-def tc_d2a33af5 : InstrItinClass;
-def tc_d63b71d1 : InstrItinClass;
-def tc_d6a805a8 : InstrItinClass;
-def tc_d95f4e98 : InstrItinClass;
-def tc_da79106e : InstrItinClass;
-def tc_dbe218dd : InstrItinClass;
-def tc_dcfee7ae : InstrItinClass;
-def tc_e17ce9ad : InstrItinClass;
-def tc_e2480a7f : InstrItinClass;
-def tc_e2c08bb4 : InstrItinClass;
-def tc_e2c31426 : InstrItinClass;
-def tc_e578178f : InstrItinClass;
-def tc_e836c161 : InstrItinClass;
-def tc_e8c7a357 : InstrItinClass;
-def tc_eb07ef6f : InstrItinClass;
-def tc_ecfaae86 : InstrItinClass;
-def tc_ef0ebaaa : InstrItinClass;
-def tc_ef2676fd : InstrItinClass;
-def tc_f027ebe9 : InstrItinClass;
-def tc_f055fbb6 : InstrItinClass;
-def tc_f1240c08 : InstrItinClass;
-def tc_f16d5b17 : InstrItinClass;
-def tc_f1aa2cdb : InstrItinClass;
-def tc_f26aa619 : InstrItinClass;
-def tc_f4608adc : InstrItinClass;
-def tc_faab1248 : InstrItinClass;
-def tc_fcee8723 : InstrItinClass;
-def tc_feb4974b : InstrItinClass;
+def tc_0077f68c : InstrItinClass;
+def tc_00afc57e : InstrItinClass;
+def tc_00e7c26e : InstrItinClass;
+def tc_03220ffa : InstrItinClass;
+def tc_038a1342 : InstrItinClass;
+def tc_04c9decc : InstrItinClass;
+def tc_05b6c987 : InstrItinClass;
+def tc_0a2b8c7c : InstrItinClass;
+def tc_0cd51c76 : InstrItinClass;
+def tc_0dc560de : InstrItinClass;
+def tc_0fc1ae07 : InstrItinClass;
+def tc_10b97e27 : InstrItinClass;
+def tc_128f96e3 : InstrItinClass;
+def tc_1372bca1 : InstrItinClass;
+def tc_1432937d : InstrItinClass;
+def tc_14cd4cfa : InstrItinClass;
+def tc_15411484 : InstrItinClass;
+def tc_16d0d8d5 : InstrItinClass;
+def tc_181af5d0 : InstrItinClass;
+def tc_1853ea6d : InstrItinClass;
+def tc_1b82a277 : InstrItinClass;
+def tc_1b9c9ee5 : InstrItinClass;
+def tc_1c0005f9 : InstrItinClass;
+def tc_1d5a38a8 : InstrItinClass;
+def tc_1e856f58 : InstrItinClass;
+def tc_20280784 : InstrItinClass;
+def tc_234a11a5 : InstrItinClass;
+def tc_238d91d2 : InstrItinClass;
+def tc_29175780 : InstrItinClass;
+def tc_29641329 : InstrItinClass;
+def tc_2a160009 : InstrItinClass;
+def tc_2b2f4060 : InstrItinClass;
+def tc_2b6f77c6 : InstrItinClass;
+def tc_2e00db30 : InstrItinClass;
+def tc_2f185f5c : InstrItinClass;
+def tc_2fc0c436 : InstrItinClass;
+def tc_351fed2d : InstrItinClass;
+def tc_3669266a : InstrItinClass;
+def tc_367f7f3d : InstrItinClass;
+def tc_36c68ad1 : InstrItinClass;
+def tc_395dc00f : InstrItinClass;
+def tc_3bc2c5d3 : InstrItinClass;
+def tc_3cb8ea06 : InstrItinClass;
+def tc_3d04548d : InstrItinClass;
+def tc_3da80ba5 : InstrItinClass;
+def tc_3e07fb90 : InstrItinClass;
+def tc_41d5298e : InstrItinClass;
+def tc_4403ca65 : InstrItinClass;
+def tc_44126683 : InstrItinClass;
+def tc_452f85af : InstrItinClass;
+def tc_481e5e5c : InstrItinClass;
+def tc_49eb22c8 : InstrItinClass;
+def tc_4ca572d4 : InstrItinClass;
+def tc_4d9914c9 : InstrItinClass;
+def tc_4d99bca9 : InstrItinClass;
+def tc_4f7cd700 : InstrItinClass;
+def tc_513bef45 : InstrItinClass;
+def tc_51b866be : InstrItinClass;
+def tc_523fcf30 : InstrItinClass;
+def tc_5274e61a : InstrItinClass;
+def tc_52d7bbea : InstrItinClass;
+def tc_53173427 : InstrItinClass;
+def tc_53bc8a6a : InstrItinClass;
+def tc_53bdb2f6 : InstrItinClass;
+def tc_540fdfbc : InstrItinClass;
+def tc_55050d58 : InstrItinClass;
+def tc_56d25411 : InstrItinClass;
+def tc_57288781 : InstrItinClass;
+def tc_594ab548 : InstrItinClass;
+def tc_5acef64a : InstrItinClass;
+def tc_5ba5997d : InstrItinClass;
+def tc_5eb851fc : InstrItinClass;
+def tc_5f6847a1 : InstrItinClass;
+def tc_60571023 : InstrItinClass;
+def tc_609d2efe : InstrItinClass;
+def tc_60d76817 : InstrItinClass;
+def tc_60f5738d : InstrItinClass;
+def tc_63fe3df7 : InstrItinClass;
+def tc_66888ded : InstrItinClass;
+def tc_6792d5ff : InstrItinClass;
+def tc_681a2300 : InstrItinClass;
+def tc_68cb12ce : InstrItinClass;
+def tc_6aa5711a : InstrItinClass;
+def tc_6ac37025 : InstrItinClass;
+def tc_6ebb4a12 : InstrItinClass;
+def tc_6efc556e : InstrItinClass;
+def tc_73043bf4 : InstrItinClass;
+def tc_746baa8e : InstrItinClass;
+def tc_74e47fd9 : InstrItinClass;
+def tc_7934b9df : InstrItinClass;
+def tc_7a830544 : InstrItinClass;
+def tc_7f881c76 : InstrItinClass;
+def tc_84df2cd3 : InstrItinClass;
+def tc_85523bcb : InstrItinClass;
+def tc_855b0b61 : InstrItinClass;
+def tc_87735c3b : InstrItinClass;
+def tc_88fa1a78 : InstrItinClass;
+def tc_897d1a9d : InstrItinClass;
+def tc_8b15472a : InstrItinClass;
+def tc_8bb285ec : InstrItinClass;
+def tc_8fd5f294 : InstrItinClass;
+def tc_8fe6b782 : InstrItinClass;
+def tc_90f3e30c : InstrItinClass;
+def tc_976ddc4f : InstrItinClass;
+def tc_97743097 : InstrItinClass;
+def tc_999d32db : InstrItinClass;
+def tc_99be14ca : InstrItinClass;
+def tc_9c00ce8d : InstrItinClass;
+def tc_9c98e8af : InstrItinClass;
+def tc_9d5941c7 : InstrItinClass;
+def tc_9ef61e5c : InstrItinClass;
+def tc_9faf76ae : InstrItinClass;
+def tc_9fdb5406 : InstrItinClass;
+def tc_a21dc435 : InstrItinClass;
+def tc_a27582fa : InstrItinClass;
+def tc_a46f0df5 : InstrItinClass;
+def tc_a788683e : InstrItinClass;
+def tc_a8acdac0 : InstrItinClass;
+def tc_a904d137 : InstrItinClass;
+def tc_adb14c66 : InstrItinClass;
+def tc_b13761ae : InstrItinClass;
+def tc_b166348b : InstrItinClass;
+def tc_b44c6e2a : InstrItinClass;
+def tc_b5a33b22 : InstrItinClass;
+def tc_b77c481f : InstrItinClass;
+def tc_b7dd427e : InstrItinClass;
+def tc_b9488031 : InstrItinClass;
+def tc_b9c0b731 : InstrItinClass;
+def tc_b9c4623f : InstrItinClass;
+def tc_bad2bcaf : InstrItinClass;
+def tc_bcc96cee : InstrItinClass;
+def tc_bd90564c : InstrItinClass;
+def tc_bde7aaf4 : InstrItinClass;
+def tc_be706f30 : InstrItinClass;
+def tc_c2f7d806 : InstrItinClass;
+def tc_c5e2426d : InstrItinClass;
+def tc_c6aa82f7 : InstrItinClass;
+def tc_c6ce9b3f : InstrItinClass;
+def tc_c6ebf8dd : InstrItinClass;
+def tc_c74f796f : InstrItinClass;
+def tc_c82dc1ff : InstrItinClass;
+def tc_caaebcba : InstrItinClass;
+def tc_cd7374a0 : InstrItinClass;
+def tc_cde8b071 : InstrItinClass;
+def tc_cf47a43f : InstrItinClass;
+def tc_cf59f215 : InstrItinClass;
+def tc_d088982c : InstrItinClass;
+def tc_d1090e34 : InstrItinClass;
+def tc_d24b2d85 : InstrItinClass;
+def tc_d580173f : InstrItinClass;
+def tc_d6bf0472 : InstrItinClass;
+def tc_d9709180 : InstrItinClass;
+def tc_d9f95eef : InstrItinClass;
+def tc_daa058fa : InstrItinClass;
+def tc_dbdffe3d : InstrItinClass;
+def tc_e0739b8c : InstrItinClass;
+def tc_e1e0a2dc : InstrItinClass;
+def tc_e1e99bfa : InstrItinClass;
+def tc_e216a5db : InstrItinClass;
+def tc_e421e012 : InstrItinClass;
+def tc_e6b38e01 : InstrItinClass;
+def tc_e7624c08 : InstrItinClass;
+def tc_e7d02c66 : InstrItinClass;
+def tc_e913dc32 : InstrItinClass;
+def tc_e9c822f7 : InstrItinClass;
+def tc_e9fae2d6 : InstrItinClass;
+def tc_ef20db1c : InstrItinClass;
+def tc_ef52ed71 : InstrItinClass;
+def tc_ef84f62f : InstrItinClass;
+def tc_f2704b9a : InstrItinClass;
+def tc_f3eaa14b : InstrItinClass;
+def tc_f47d212f : InstrItinClass;
+def tc_f49e76f4 : InstrItinClass;
+def tc_f4f43fb5 : InstrItinClass;
+def tc_f7dd9c9f : InstrItinClass;
+def tc_f86c328a : InstrItinClass;
+def tc_f8eeed7a : InstrItinClass;
+def tc_fcab4871 : InstrItinClass;
+def tc_ff9ee76e : InstrItinClass;
class DepScalarItinV4 {
list<InstrItinData> DepScalarItinV4_list = [
- InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]> ];
+ InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]> ];
}
class DepScalarItinV5 {
list<InstrItinData> DepScalarItinV5_list = [
- InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>,
- InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>,
- InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>,
- InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]> ];
+ InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>,
+ InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>,
+ InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]> ];
}
class DepScalarItinV55 {
list<InstrItinData> DepScalarItinV55_list = [
- InstrItinData <tc_049dfb74, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
+ InstrItinData <tc_0077f68c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_0767081f, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ InstrItinData <tc_00afc57e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_07ac815d, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_00e7c26e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_090485bb, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_03220ffa, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_09c86199, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_038a1342, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_09faec3b, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ InstrItinData <tc_04c9decc, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_0cb867f2, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [4, 2, 2],
+ InstrItinData <tc_05b6c987, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1000eb10, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 2],
+ InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_128719e8, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ InstrItinData <tc_0cd51c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_136c4786, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_14da557c, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1b6011fb, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ InstrItinData <tc_0dc560de, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1b834fe7, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1e062b18, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1e69aa99, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_0fc1ae07, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_1f9668cc, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [3, 1],
+ InstrItinData <tc_10b97e27, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1fe8323c, /*tc_2*/
- [InstrStage<1, [SLOT3]>], [4, 2],
+ InstrItinData <tc_128f96e3, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_20a8e109, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_1372bca1, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_210b2456, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_1432937d, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_251c87b2, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_14cd4cfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_261d9b78, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_15411484, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_28d296df, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+ InstrItinData <tc_16d0d8d5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_29c14515, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [4, 1],
+ InstrItinData <tc_181af5d0, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2aaab1e0, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_2c8fe5ae, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ InstrItinData <tc_1853ea6d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2d1e6f5c, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_2e55aa16, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_30665cb0, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1],
+ InstrItinData <tc_1b82a277, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
[Hex_FWD]>,
- InstrItinData <tc_336e698c, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ InstrItinData <tc_1b9c9ee5, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_34e882a4, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [1],
- [Hex_FWD]>,
+ InstrItinData <tc_1c0005f9, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_35fb9d13, /*tc_2early*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
+ InstrItinData <tc_1d5a38a8, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_37326008, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_1e856f58, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3993c58b, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 3, 1],
+ InstrItinData <tc_20280784, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_234a11a5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_238d91d2, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3b4892c6, /*tc_3x*/
+ InstrItinData <tc_29175780, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3bea1824, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ InstrItinData <tc_29641329, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3c10f809, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2a160009, /*tc_2early*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_3d905451, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ InstrItinData <tc_2b2f4060, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3e61d314, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [1, 3, 2],
+ InstrItinData <tc_2b6f77c6, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3eab77bd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2e00db30, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_43068634, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2f185f5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_45631a8d, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ InstrItinData <tc_2fc0c436, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_47ab9233, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_47f0b7ad, /*tc_2early*/
+ InstrItinData <tc_351fed2d, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_485bb57c, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_4997da4a, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [1],
+ InstrItinData <tc_3669266a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_511f28f6, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_367f7f3d, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_537e2013, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_36c68ad1, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [],
+ []>,
- InstrItinData <tc_53ee6546, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ InstrItinData <tc_395dc00f, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 3, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_548f402d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3bc2c5d3, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_5625c6c1, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3cb8ea06, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_580a779c, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3d04548d, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_583510c7, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ InstrItinData <tc_3da80ba5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3e07fb90, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41d5298e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5d806107, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4403ca65, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5fa2857c, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+ InstrItinData <tc_44126683, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5fe9fcd0, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_452f85af, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_6264c5e0, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ InstrItinData <tc_481e5e5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_639d93ee, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
-
- InstrItinData <tc_63cd9d2d, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_49eb22c8, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_65dc7cc4, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_69bb508b, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4ca572d4, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_6c52d277, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ InstrItinData <tc_4d9914c9, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6c576d46, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ InstrItinData <tc_4d99bca9, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_70cabf66, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ InstrItinData <tc_4f7cd700, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7639d4b0, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_7675c0e9, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_513bef45, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_76c4c5ef, /*tc_2*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_51b866be, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_77781686, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ InstrItinData <tc_523fcf30, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_78b3c689, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_7986ba30, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_7bc567a7, /*tc_st*/
+ InstrItinData <tc_5274e61a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7c2dcd4d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
- [Hex_FWD]>,
+ InstrItinData <tc_52d7bbea, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
- InstrItinData <tc_7ca2ea10, /*tc_1*/
+ InstrItinData <tc_53173427, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_53bc8a6a, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7d01cbdc, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ InstrItinData <tc_53bdb2f6, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7d9a56cd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_81a23d44, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_540fdfbc, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_821c4233, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ InstrItinData <tc_55050d58, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_82f0f122, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [4, 1],
+ InstrItinData <tc_56d25411, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_84630363, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
+ InstrItinData <tc_57288781, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_86442910, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [],
- []>,
-
- InstrItinData <tc_87601822, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_594ab548, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_88fa2da6, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5acef64a, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8c8041e6, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ InstrItinData <tc_5ba5997d, /*tc_2*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8cb685d9, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_8def9c57, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5eb851fc, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8f0a6bad, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5f6847a1, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8fab9ac3, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ InstrItinData <tc_60571023, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_92d1833c, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+ InstrItinData <tc_609d2efe, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_94e6ffd9, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_60d76817, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_95c54f8b, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
-
- InstrItinData <tc_9a13af9d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ InstrItinData <tc_60f5738d, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_9b73d261, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ InstrItinData <tc_63fe3df7, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c18c9a5, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_66888ded, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c68db63, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_9ce7a5ab, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 2, 1],
+ InstrItinData <tc_6792d5ff, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9da3628f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_681a2300, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_9dafb7d3, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_68cb12ce, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6aa5711a, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6ac37025, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9df8b0dc, /*tc_2early*/
+ InstrItinData <tc_6ebb4a12, /*tc_2early*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9e86015f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 3],
+ InstrItinData <tc_6efc556e, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_73043bf4, /*tc_2early*/
+ [InstrStage<1, [SLOT3]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9f518242, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_746baa8e, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a12a5971, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_74e47fd9, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a1fb80e1, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
+ InstrItinData <tc_7934b9df, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a333d2a9, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_7a830544, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a4567c39, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+ InstrItinData <tc_7f881c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_84df2cd3, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a87879e8, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_85523bcb, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a9c993d9, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ InstrItinData <tc_855b0b61, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_aad55963, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_87735c3b, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ab1b5e74, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_88fa1a78, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae0722f7, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_ae2c2dc2, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+ InstrItinData <tc_897d1a9d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae762521, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_8b15472a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b08b653e, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
+ InstrItinData <tc_8bb285ec, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_b08be45e, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ InstrItinData <tc_8fd5f294, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b0f50e3c, /*tc_2*/
+ InstrItinData <tc_8fe6b782, /*tc_2*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b189ad4c, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2],
- [Hex_FWD]>,
-
- InstrItinData <tc_b324366f, /*tc_2early*/
- [InstrStage<1, [SLOT3]>], [1, 2],
+ InstrItinData <tc_90f3e30c, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5bfaa60, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ InstrItinData <tc_976ddc4f, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_97743097, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5f5a094, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+ InstrItinData <tc_999d32db, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_99be14ca, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b86c7e8b, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_9c00ce8d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9c98e8af, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_baccf077, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+ InstrItinData <tc_9d5941c7, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bc5561d8, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+ InstrItinData <tc_9ef61e5c, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bcf0e36e, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [],
- []>,
+ InstrItinData <tc_9faf76ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_bd16579e, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_9fdb5406, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_be995eaf, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a21dc435, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bf6fa601, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a27582fa, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_c0cd91a8, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a46f0df5, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c14739d5, /*tc_st*/
+ InstrItinData <tc_a788683e, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c1dbc916, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ InstrItinData <tc_a8acdac0, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a904d137, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c58f771a, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_adb14c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c85212ca, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b13761ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
- InstrItinData <tc_c8f9a6f6, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ InstrItinData <tc_b166348b, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ca280e8b, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b44c6e2a, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_cbe45117, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_b5a33b22, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_cd321066, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_b77c481f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d108a090, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
+ InstrItinData <tc_b7dd427e, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9488031, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d1b5a4b6, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ InstrItinData <tc_b9c0b731, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d2609065, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+ InstrItinData <tc_b9c4623f, /*tc_2*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d267fa19, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [],
- []>,
-
- InstrItinData <tc_d2a33af5, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bad2bcaf, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d63b71d1, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bcc96cee, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d6a805a8, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 1],
+ InstrItinData <tc_bd90564c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d95f4e98, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_da79106e, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ InstrItinData <tc_bde7aaf4, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dbe218dd, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [3, 2],
+ InstrItinData <tc_be706f30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dcfee7ae, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 2],
+ InstrItinData <tc_c2f7d806, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e17ce9ad, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_c5e2426d, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2480a7f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_c6aa82f7, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ce9b3f, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c08bb4, /*tc_2early*/
+ InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c31426, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_c74f796f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e578178f, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_c82dc1ff, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_e836c161, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_caaebcba, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e8c7a357, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_cd7374a0, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_eb07ef6f, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+ InstrItinData <tc_cde8b071, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ecfaae86, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
- [Hex_FWD]>,
+ InstrItinData <tc_cf47a43f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ef0ebaaa, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [1, 2],
+ InstrItinData <tc_cf59f215, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ef2676fd, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
-
- InstrItinData <tc_f027ebe9, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_d088982c, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f055fbb6, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 1],
+ InstrItinData <tc_d1090e34, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1240c08, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_d24b2d85, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f16d5b17, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_d580173f, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1aa2cdb, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_d6bf0472, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f26aa619, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
- [Hex_FWD]>,
+ InstrItinData <tc_d9709180, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9f95eef, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f4608adc, /*tc_3stall*/
+ InstrItinData <tc_daa058fa, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_faab1248, /*tc_2*/
+ InstrItinData <tc_dbdffe3d, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_fcee8723, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_feb4974b, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>
- ];
-}
+ InstrItinData <tc_e0739b8c, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
-class DepScalarItinV60 {
- list<InstrItinData> DepScalarItinV60_list = [
- InstrItinData <tc_049dfb74, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
- [Hex_FWD]>,
+ InstrItinData <tc_e1e0a2dc, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
- InstrItinData <tc_0767081f, /*tc_2early*/
+ InstrItinData <tc_e1e99bfa, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_07ac815d, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_090485bb, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_09c86199, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_09faec3b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_0cb867f2, /*tc_ld*/
+ InstrItinData <tc_e216a5db, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1000eb10, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_128719e8, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ InstrItinData <tc_e421e012, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_136c4786, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_e6b38e01, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_14da557c, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_e7624c08, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [3],
+ [Hex_FWD]>,
- InstrItinData <tc_1b6011fb, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ InstrItinData <tc_e7d02c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1b834fe7, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1e062b18, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1e69aa99, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ InstrItinData <tc_e913dc32, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1f9668cc, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [3, 1],
+ InstrItinData <tc_e9c822f7, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e9fae2d6, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1fe8323c, /*tc_2*/
+ InstrItinData <tc_ef20db1c, /*tc_3x*/
[InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_20a8e109, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ InstrItinData <tc_ef52ed71, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_210b2456, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+ InstrItinData <tc_ef84f62f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_251c87b2, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_f2704b9a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_261d9b78, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_f3eaa14b, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_28d296df, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+ InstrItinData <tc_f47d212f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_29c14515, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [4, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_f49e76f4, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2aaab1e0, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_f4f43fb5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2c8fe5ae, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ InstrItinData <tc_f7dd9c9f, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2d1e6f5c, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+ InstrItinData <tc_f86c328a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2e55aa16, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_f8eeed7a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_30665cb0, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1],
+ InstrItinData <tc_fcab4871, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_ff9ee76e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 3],
+ [Hex_FWD, Hex_FWD]>
+ ];
+}
+
+class DepScalarItinV60 {
+ list<InstrItinData> DepScalarItinV60_list = [
+ InstrItinData <tc_0077f68c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_336e698c, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_00afc57e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_34e882a4, /*tc_ld*/
+ InstrItinData <tc_00e7c26e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_35fb9d13, /*tc_2early*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
+ InstrItinData <tc_03220ffa, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_37326008, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_038a1342, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3993c58b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 3, 2],
+ InstrItinData <tc_04c9decc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3b4892c6, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_3bea1824, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+ InstrItinData <tc_05b6c987, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3c10f809, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_3d905451, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_3e61d314, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [2, 3, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3eab77bd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+ InstrItinData <tc_0cd51c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_43068634, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_45631a8d, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ InstrItinData <tc_0dc560de, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_47ab9233, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_0fc1ae07, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_47f0b7ad, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+ InstrItinData <tc_10b97e27, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_485bb57c, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_128f96e3, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_4997da4a, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [1],
- [Hex_FWD]>,
-
- InstrItinData <tc_511f28f6, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_1372bca1, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_537e2013, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_1432937d, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_53ee6546, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_548f402d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_5625c6c1, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_14cd4cfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_580a779c, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_15411484, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_583510c7, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ InstrItinData <tc_16d0d8d5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5d806107, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_5fa2857c, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_181af5d0, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5fe9fcd0, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ InstrItinData <tc_1853ea6d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6264c5e0, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_639d93ee, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2],
+ InstrItinData <tc_1b82a277, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
[Hex_FWD]>,
- InstrItinData <tc_63cd9d2d, /*tc_2*/
+ InstrItinData <tc_1b9c9ee5, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_65dc7cc4, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_69bb508b, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_6c52d277, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ InstrItinData <tc_1c0005f9, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6c576d46, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ InstrItinData <tc_1d5a38a8, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_70cabf66, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_1e856f58, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7639d4b0, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_20280784, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7675c0e9, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_234a11a5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_76c4c5ef, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_238d91d2, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_77781686, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_78b3c689, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_29175780, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7986ba30, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 2, 3],
+ InstrItinData <tc_29641329, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7bc567a7, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2a160009, /*tc_2early*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_7c2dcd4d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
- [Hex_FWD]>,
+ InstrItinData <tc_2b2f4060, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7ca2ea10, /*tc_2*/
+ InstrItinData <tc_2b6f77c6, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7d01cbdc, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_7d9a56cd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2e00db30, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_81a23d44, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_2f185f5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_821c4233, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2fc0c436, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_82f0f122, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [4, 1],
+ InstrItinData <tc_351fed2d, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_84630363, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3669266a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_367f7f3d, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_86442910, /*tc_ld*/
+ InstrItinData <tc_36c68ad1, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [],
[]>,
- InstrItinData <tc_87601822, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_395dc00f, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_88fa2da6, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3cb8ea06, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8c8041e6, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3d04548d, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8cb685d9, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3da80ba5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_8def9c57, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+ InstrItinData <tc_3e07fb90, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8f0a6bad, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ InstrItinData <tc_41d5298e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8fab9ac3, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ InstrItinData <tc_4403ca65, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_92d1833c, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+ InstrItinData <tc_44126683, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_94e6ffd9, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_95c54f8b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
-
- InstrItinData <tc_9a13af9d, /*tc_1*/
+ InstrItinData <tc_452f85af, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_9b73d261, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_481e5e5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c18c9a5, /*tc_1*/
+ InstrItinData <tc_49eb22c8, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c68db63, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4ca572d4, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ InstrItinData <tc_4d9914c9, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4d99bca9, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9da3628f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4f7cd700, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9dafb7d3, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_513bef45, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9df8b0dc, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+ InstrItinData <tc_51b866be, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9e86015f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 3],
+ InstrItinData <tc_523fcf30, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5274e61a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_52d7bbea, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_53173427, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9f518242, /*tc_1*/
+ InstrItinData <tc_53bc8a6a, /*tc_2early*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a12a5971, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_53bdb2f6, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a1fb80e1, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
+ InstrItinData <tc_540fdfbc, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_55050d58, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_56d25411, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a333d2a9, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_57288781, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a4567c39, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+ InstrItinData <tc_594ab548, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a87879e8, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5acef64a, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a9c993d9, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ InstrItinData <tc_5ba5997d, /*tc_2*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_aad55963, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ab1b5e74, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5f6847a1, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae0722f7, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+ InstrItinData <tc_60571023, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae2c2dc2, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+ InstrItinData <tc_609d2efe, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae762521, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_60d76817, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_b08b653e, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
+ InstrItinData <tc_60f5738d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_b08be45e, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ InstrItinData <tc_63fe3df7, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_66888ded, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b0f50e3c, /*tc_2*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_6792d5ff, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b189ad4c, /*tc_3stall*/
+ InstrItinData <tc_681a2300, /*tc_3stall*/
[InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_b324366f, /*tc_2early*/
- [InstrStage<1, [SLOT3]>], [1, 2],
+ InstrItinData <tc_68cb12ce, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5bfaa60, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ InstrItinData <tc_6aa5711a, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5f5a094, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+ InstrItinData <tc_6ac37025, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b86c7e8b, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_6ebb4a12, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6efc556e, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_73043bf4, /*tc_2early*/
+ [InstrStage<1, [SLOT3]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_baccf077, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_746baa8e, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bc5561d8, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+ InstrItinData <tc_74e47fd9, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bcf0e36e, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [],
- []>,
+ InstrItinData <tc_7934b9df, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bd16579e, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_7a830544, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_be995eaf, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_bf6fa601, /*tc_ld*/
+ InstrItinData <tc_7f881c76, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c0cd91a8, /*tc_2*/
+ InstrItinData <tc_84df2cd3, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c14739d5, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+ InstrItinData <tc_85523bcb, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_855b0b61, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_87735c3b, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_88fa1a78, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c1dbc916, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ InstrItinData <tc_897d1a9d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8b15472a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8bb285ec, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_8fd5f294, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8fe6b782, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_90f3e30c, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c58f771a, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+ InstrItinData <tc_976ddc4f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c85212ca, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+ InstrItinData <tc_97743097, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_999d32db, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_99be14ca, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c8f9a6f6, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ InstrItinData <tc_9c00ce8d, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ca280e8b, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_9c98e8af, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_cbe45117, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2],
+ InstrItinData <tc_9d5941c7, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9ef61e5c, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9faf76ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_cd321066, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_9fdb5406, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d108a090, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a21dc435, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d1b5a4b6, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ InstrItinData <tc_a27582fa, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_a46f0df5, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a788683e, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a8acdac0, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d2609065, /*tc_1*/
+ InstrItinData <tc_a904d137, /*tc_1*/
[InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d267fa19, /*tc_2early*/
+ InstrItinData <tc_adb14c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b13761ae, /*tc_2early*/
[InstrStage<1, [SLOT2]>], [],
[]>,
- InstrItinData <tc_d2a33af5, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b166348b, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d63b71d1, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_b44c6e2a, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d6a805a8, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [2, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b5a33b22, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d95f4e98, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+ InstrItinData <tc_b77c481f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b7dd427e, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_da79106e, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ InstrItinData <tc_b9488031, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dbe218dd, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b9c0b731, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dcfee7ae, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2],
+ InstrItinData <tc_b9c4623f, /*tc_2*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e17ce9ad, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_e2480a7f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+ InstrItinData <tc_bad2bcaf, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c08bb4, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bcc96cee, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c31426, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_bd90564c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e578178f, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e836c161, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+ InstrItinData <tc_be706f30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e8c7a357, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ InstrItinData <tc_c2f7d806, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_eb07ef6f, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [1, 2],
+ InstrItinData <tc_c5e2426d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ecfaae86, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
- [Hex_FWD]>,
+ InstrItinData <tc_c6aa82f7, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ef0ebaaa, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [1, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ef2676fd, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
+ InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f027ebe9, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [2],
+ InstrItinData <tc_c74f796f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c82dc1ff, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_f055fbb6, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 1],
+ InstrItinData <tc_caaebcba, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cd7374a0, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cde8b071, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1240c08, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_cf47a43f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f16d5b17, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_cf59f215, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1aa2cdb, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_d088982c, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f26aa619, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
- [Hex_FWD]>,
+ InstrItinData <tc_d1090e34, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d24b2d85, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d580173f, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d6bf0472, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9709180, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9f95eef, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_daa058fa, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_dbdffe3d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e0739b8c, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
+
+ InstrItinData <tc_e1e99bfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e216a5db, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e421e012, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e6b38e01, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e7624c08, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e7d02c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e913dc32, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e9c822f7, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e9fae2d6, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef20db1c, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef52ed71, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef84f62f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f2704b9a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f3eaa14b, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f47d212f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f49e76f4, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f4f43fb5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f7dd9c9f, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f86c328a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f8eeed7a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_fcab4871, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_ff9ee76e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 3],
+ [Hex_FWD, Hex_FWD]>
+ ];
+}
+
+class DepScalarItinV60se {
+ list<InstrItinData> DepScalarItinV60se_list = [
+ InstrItinData <tc_0077f68c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_00afc57e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_00e7c26e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_03220ffa, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_038a1342, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_04c9decc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_05b6c987, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0cd51c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0dc560de, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0fc1ae07, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_10b97e27, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_128f96e3, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1372bca1, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1432937d, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_14cd4cfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_15411484, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_16d0d8d5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_181af5d0, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1853ea6d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1b82a277, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_1b9c9ee5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1c0005f9, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1d5a38a8, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1e856f58, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_20280784, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_234a11a5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_238d91d2, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_29175780, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_29641329, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2a160009, /*tc_2early*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [],
+ []>,
+
+ InstrItinData <tc_2b2f4060, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2b6f77c6, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2e00db30, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_2f185f5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2fc0c436, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_351fed2d, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3669266a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_367f7f3d, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_36c68ad1, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [],
+ []>,
+
+ InstrItinData <tc_395dc00f, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3cb8ea06, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3d04548d, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3da80ba5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3e07fb90, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41d5298e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4403ca65, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_44126683, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_452f85af, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_481e5e5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_49eb22c8, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4ca572d4, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_4d9914c9, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4d99bca9, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4f7cd700, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_513bef45, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_51b866be, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_523fcf30, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5274e61a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_52d7bbea, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [],
+ []>,
+
+ InstrItinData <tc_53173427, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_53bc8a6a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_53bdb2f6, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_540fdfbc, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_55050d58, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_56d25411, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_57288781, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_594ab548, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5acef64a, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5ba5997d, /*tc_2*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5f6847a1, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_60571023, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_609d2efe, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_60d76817, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_60f5738d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_63fe3df7, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_66888ded, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6792d5ff, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_681a2300, /*tc_3stall*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_68cb12ce, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6aa5711a, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6ac37025, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6ebb4a12, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6efc556e, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_73043bf4, /*tc_2early*/
+ [InstrStage<1, [SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_746baa8e, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_74e47fd9, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7934b9df, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7a830544, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7f881c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_84df2cd3, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_85523bcb, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_855b0b61, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_87735c3b, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_88fa1a78, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_897d1a9d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8b15472a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8bb285ec, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_8fd5f294, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8fe6b782, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_90f3e30c, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_976ddc4f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_97743097, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_999d32db, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_99be14ca, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9c00ce8d, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9c98e8af, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9d5941c7, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9ef61e5c, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9faf76ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_9fdb5406, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a21dc435, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a27582fa, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_a46f0df5, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a788683e, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a8acdac0, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a904d137, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_adb14c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b13761ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
+
+ InstrItinData <tc_b166348b, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b44c6e2a, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b5a33b22, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b77c481f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b7dd427e, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9488031, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9c0b731, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9c4623f, /*tc_2*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bad2bcaf, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bcc96cee, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bd90564c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_be706f30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c2f7d806, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c5e2426d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6aa82f7, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ebf8dd, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c74f796f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c82dc1ff, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_caaebcba, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cd7374a0, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cde8b071, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cf47a43f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cf59f215, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d088982c, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d1090e34, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d24b2d85, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d580173f, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d6bf0472, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9709180, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9f95eef, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_daa058fa, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_dbdffe3d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e0739b8c, /*tc_2early*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2], 0>,
+ InstrStage<1, [CVI_ST]>], [],
+ []>,
+
+ InstrItinData <tc_e1e99bfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e216a5db, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e421e012, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e6b38e01, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e7624c08, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e7d02c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e913dc32, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e9c822f7, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e9fae2d6, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [CVI_ST]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef20db1c, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef52ed71, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef84f62f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f2704b9a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f3eaa14b, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f47d212f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f49e76f4, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f4f43fb5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f7dd9c9f, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f86c328a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f8eeed7a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_fcab4871, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0], 0>,
+ InstrStage<1, [CVI_ST]>], [],
+ []>,
+
+ InstrItinData <tc_ff9ee76e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 3],
+ [Hex_FWD, Hex_FWD]>
+ ];
+}
+
+class DepScalarItinV62 {
+ list<InstrItinData> DepScalarItinV62_list = [
+ InstrItinData <tc_0077f68c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_00afc57e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_00e7c26e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_03220ffa, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_038a1342, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_04c9decc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_05b6c987, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0cd51c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0dc560de, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0fc1ae07, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_10b97e27, /*tc_3*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_128f96e3, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1372bca1, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1432937d, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_14cd4cfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_15411484, /*tc_3*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_16d0d8d5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_181af5d0, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1853ea6d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1b82a277, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_1b9c9ee5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1c0005f9, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1d5a38a8, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_1e856f58, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_20280784, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_234a11a5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_238d91d2, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_29175780, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_29641329, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2a160009, /*tc_2early*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_2b2f4060, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2b6f77c6, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2e00db30, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_2f185f5c, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_2fc0c436, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_351fed2d, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3669266a, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_367f7f3d, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_36c68ad1, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [],
+ []>,
+
+ InstrItinData <tc_395dc00f, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3cb8ea06, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3d04548d, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3da80ba5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3e07fb90, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41d5298e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4403ca65, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_44126683, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_452f85af, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_481e5e5c, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_49eb22c8, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4ca572d4, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_4d9914c9, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4d99bca9, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_4f7cd700, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_513bef45, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_51b866be, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_523fcf30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5274e61a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_52d7bbea, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_53173427, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_53bc8a6a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_53bdb2f6, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_540fdfbc, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_55050d58, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_56d25411, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_57288781, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_594ab548, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5acef64a, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5ba5997d, /*tc_2*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_5f6847a1, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_60571023, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_609d2efe, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_60d76817, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_60f5738d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_63fe3df7, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_66888ded, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6792d5ff, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_681a2300, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_68cb12ce, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6aa5711a, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6ac37025, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6ebb4a12, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_6efc556e, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
+
+ InstrItinData <tc_73043bf4, /*tc_2early*/
+ [InstrStage<1, [SLOT3]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_746baa8e, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_74e47fd9, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7934b9df, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7a830544, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7f881c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_84df2cd3, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_85523bcb, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_855b0b61, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_87735c3b, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_88fa1a78, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_897d1a9d, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8b15472a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8bb285ec, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_8fd5f294, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8fe6b782, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_90f3e30c, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_976ddc4f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_97743097, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_999d32db, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_99be14ca, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9c00ce8d, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9c98e8af, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9d5941c7, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9ef61e5c, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_9faf76ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_9fdb5406, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a21dc435, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a27582fa, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_a46f0df5, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a788683e, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a8acdac0, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_a904d137, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_adb14c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b13761ae, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
+
+ InstrItinData <tc_b166348b, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b44c6e2a, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b5a33b22, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b77c481f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b7dd427e, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9488031, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9c0b731, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9c4623f, /*tc_2*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bad2bcaf, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bcc96cee, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bd90564c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_be706f30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c2f7d806, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c5e2426d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6aa82f7, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ebf8dd, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c74f796f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c82dc1ff, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_caaebcba, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cd7374a0, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cde8b071, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cf47a43f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_cf59f215, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d088982c, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d1090e34, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d24b2d85, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d580173f, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d6bf0472, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9709180, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9f95eef, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_daa058fa, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_dbdffe3d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e0739b8c, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
+
+ InstrItinData <tc_e1e99bfa, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e216a5db, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e421e012, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e6b38e01, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e7624c08, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e7d02c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e913dc32, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e9c822f7, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_e9fae2d6, /*tc_2early*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef20db1c, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef52ed71, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_ef84f62f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f2704b9a, /*tc_2early*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f3eaa14b, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f47d212f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f49e76f4, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f4f43fb5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f7dd9c9f, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f86c328a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f8eeed7a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_fcab4871, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_ff9ee76e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 3],
+ [Hex_FWD, Hex_FWD]>
+ ];
+}
+
+class DepScalarItinV65 {
+ list<InstrItinData> DepScalarItinV65_list = [
+ InstrItinData <tc_0077f68c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_00afc57e, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_00e7c26e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_03220ffa, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_038a1342, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_04c9decc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_05b6c987, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0a2b8c7c, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0cd51c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0dc560de, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_0fc1ae07, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_10b97e27, /*tc_3*/
+ [InstrStage<1, [SLOT2]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f4608adc, /*tc_3stall*/
+ InstrItinData <tc_128f96e3, /*tc_3stall*/
[InstrStage<1, [SLOT0]>], [1, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_faab1248, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_1372bca1, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_fcee8723, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_1432937d, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_feb4974b, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>
- ];
-}
+ InstrItinData <tc_14cd4cfa, /*tc_2early*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
-class DepScalarItinV62 {
- list<InstrItinData> DepScalarItinV62_list = [
- InstrItinData <tc_049dfb74, /*tc_2early*/
+ InstrItinData <tc_15411484, /*tc_3*/
[InstrStage<1, [SLOT2]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_0767081f, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_07ac815d, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_090485bb, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ InstrItinData <tc_16d0d8d5, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_09c86199, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_181af5d0, /*tc_1*/
+ [InstrStage<1, [SLOT2]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_09faec3b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ InstrItinData <tc_1853ea6d, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_0cb867f2, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [4, 2, 2],
+ InstrItinData <tc_1b82a277, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_1b9c9ee5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1000eb10, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 2],
+ InstrItinData <tc_1c0005f9, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_128719e8, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_136c4786, /*tc_ld*/
+ InstrItinData <tc_1d5a38a8, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_14da557c, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1b6011fb, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1b834fe7, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1e062b18, /*tc_1*/
+ InstrItinData <tc_1e856f58, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1e69aa99, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_1f9668cc, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [3, 1],
+ InstrItinData <tc_20280784, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_1fe8323c, /*tc_2*/
- [InstrStage<1, [SLOT3]>], [4, 2],
+ InstrItinData <tc_234a11a5, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_20a8e109, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_210b2456, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_251c87b2, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_238d91d2, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_261d9b78, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_29175780, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_28d296df, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_29641329, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_29c14515, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [4, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2a160009, /*tc_2early*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_2aaab1e0, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ InstrItinData <tc_2b2f4060, /*tc_2latepred*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2c8fe5ae, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 2, 3],
+ InstrItinData <tc_2b6f77c6, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_2d1e6f5c, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2e00db30, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
- InstrItinData <tc_2e55aa16, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_2f185f5c, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_30665cb0, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1],
- [Hex_FWD]>,
+ InstrItinData <tc_2fc0c436, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_336e698c, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_351fed2d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_34e882a4, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [1],
+ InstrItinData <tc_3669266a, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_35fb9d13, /*tc_2early*/
+ InstrItinData <tc_367f7f3d, /*tc_st*/
[InstrStage<1, [SLOT0]>], [],
[]>,
- InstrItinData <tc_37326008, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_36c68ad1, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [],
+ []>,
- InstrItinData <tc_3993c58b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 3, 2],
+ InstrItinData <tc_395dc00f, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 3, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3b4892c6, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [4, 2],
+ InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_3cb8ea06, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3bea1824, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_3d04548d, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_3da80ba5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_3c10f809, /*tc_2*/
+ InstrItinData <tc_3e07fb90, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_41d5298e, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3d905451, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4403ca65, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3e61d314, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [2, 3, 2],
+ InstrItinData <tc_44126683, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_3eab77bd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_452f85af, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_43068634, /*tc_2early*/
+ InstrItinData <tc_481e5e5c, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_45631a8d, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_47ab9233, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_49eb22c8, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_47f0b7ad, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_4ca572d4, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_485bb57c, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_4d9914c9, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_4997da4a, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [1],
- [Hex_FWD]>,
-
- InstrItinData <tc_511f28f6, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_4d99bca9, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_537e2013, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_4f7cd700, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_53ee6546, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ InstrItinData <tc_513bef45, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_548f402d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_51b866be, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5625c6c1, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_523fcf30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_580a779c, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5274e61a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_583510c7, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_52d7bbea, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
+ []>,
- InstrItinData <tc_5d806107, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_53173427, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5fa2857c, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2],
+ InstrItinData <tc_53bc8a6a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_5fe9fcd0, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1],
+ InstrItinData <tc_53bdb2f6, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6264c5e0, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_639d93ee, /*tc_3*/
- [InstrStage<1, [SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
-
- InstrItinData <tc_63cd9d2d, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ InstrItinData <tc_540fdfbc, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_65dc7cc4, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_55050d58, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_69bb508b, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_56d25411, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6c52d277, /*tc_st*/
+ InstrItinData <tc_57288781, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_6c576d46, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_594ab548, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_70cabf66, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5acef64a, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7639d4b0, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5ba5997d, /*tc_2*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7675c0e9, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_5eb851fc, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [2, 3, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_76c4c5ef, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_5f6847a1, /*tc_2latepred*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_77781686, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
+ InstrItinData <tc_60571023, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_78b3c689, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_7986ba30, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 2, 3],
+ InstrItinData <tc_609d2efe, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7bc567a7, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_60d76817, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [],
+ []>,
- InstrItinData <tc_7c2dcd4d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
+ InstrItinData <tc_60f5738d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [1],
[Hex_FWD]>,
- InstrItinData <tc_7ca2ea10, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_63fe3df7, /*tc_latepredldaia*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7d01cbdc, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [4, 1, 1],
+ InstrItinData <tc_66888ded, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_7d9a56cd, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_81a23d44, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_821c4233, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
+ InstrItinData <tc_6792d5ff, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_82f0f122, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [4, 1],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_681a2300, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [2],
+ [Hex_FWD]>,
- InstrItinData <tc_84630363, /*tc_3*/
- [InstrStage<1, [SLOT2]>], [2, 1],
+ InstrItinData <tc_68cb12ce, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_86442910, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [],
- []>,
-
- InstrItinData <tc_87601822, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_88fa2da6, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_6aa5711a, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8c8041e6, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ InstrItinData <tc_6ac37025, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_8cb685d9, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_8def9c57, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_8f0a6bad, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_8fab9ac3, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_92d1833c, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2],
+ InstrItinData <tc_6ebb4a12, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_94e6ffd9, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_95c54f8b, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [],
+ InstrItinData <tc_6efc556e, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
[]>,
- InstrItinData <tc_9a13af9d, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_73043bf4, /*tc_1*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9b73d261, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ InstrItinData <tc_746baa8e, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_74e47fd9, /*tc_latepredstaia*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c18c9a5, /*tc_1*/
+ InstrItinData <tc_7934b9df, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_7a830544, /*tc_1*/
[InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9c68db63, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2, 2],
+ InstrItinData <tc_7f881c76, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9da3628f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 1, 2, 3],
+ InstrItinData <tc_84df2cd3, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9dafb7d3, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_85523bcb, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9df8b0dc, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
+ InstrItinData <tc_855b0b61, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9e86015f, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [2, 3],
+ InstrItinData <tc_87735c3b, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_88fa1a78, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_9f518242, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_897d1a9d, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a12a5971, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2],
+ InstrItinData <tc_8b15472a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a1fb80e1, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2, 1],
+ InstrItinData <tc_8bb285ec, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1],
+ [Hex_FWD]>,
+
+ InstrItinData <tc_8fd5f294, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_8fe6b782, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_90f3e30c, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a333d2a9, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_976ddc4f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a4567c39, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_97743097, /*tc_1*/
+ [InstrStage<1, [SLOT2]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_a87879e8, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_999d32db, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_a9c993d9, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
+ InstrItinData <tc_99be14ca, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_aad55963, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_9c00ce8d, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ab1b5e74, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
+ InstrItinData <tc_9c98e8af, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae0722f7, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
+ InstrItinData <tc_9d5941c7, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ae2c2dc2, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_ae762521, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+ InstrItinData <tc_9ef61e5c, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b08b653e, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [1],
+ InstrItinData <tc_9faf76ae, /*tc_1*/
+ [InstrStage<1, [SLOT2]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_b08be45e, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_9fdb5406, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b0f50e3c, /*tc_2*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a21dc435, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b189ad4c, /*tc_3stall*/
- [InstrStage<1, [SLOT2]>], [2],
+ InstrItinData <tc_a27582fa, /*tc_3*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [2],
[Hex_FWD]>,
- InstrItinData <tc_b324366f, /*tc_2early*/
- [InstrStage<1, [SLOT3]>], [1, 2],
+ InstrItinData <tc_a46f0df5, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5bfaa60, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
+ InstrItinData <tc_a788683e, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b5f5a094, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_a8acdac0, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_b86c7e8b, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_a904d137, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_baccf077, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_bc5561d8, /*tc_3x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2],
+ InstrItinData <tc_adb14c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bcf0e36e, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [],
+ InstrItinData <tc_b13761ae, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [],
[]>,
- InstrItinData <tc_bd16579e, /*tc_2*/
+ InstrItinData <tc_b166348b, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b44c6e2a, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_be995eaf, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_b5a33b22, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [4, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_bf6fa601, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
+ InstrItinData <tc_b77c481f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c0cd91a8, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ InstrItinData <tc_b7dd427e, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9488031, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_b9c0b731, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c14739d5, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 2],
+ InstrItinData <tc_b9c4623f, /*tc_2*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c1dbc916, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bad2bcaf, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c58f771a, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_bcc96cee, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c85212ca, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2],
+ InstrItinData <tc_bd90564c, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_bde7aaf4, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_c8f9a6f6, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_be706f30, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ca280e8b, /*tc_2*/
+ InstrItinData <tc_c2f7d806, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_cbe45117, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [2],
- [Hex_FWD]>,
+ InstrItinData <tc_c5e2426d, /*tc_3stall*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_cd321066, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
+ InstrItinData <tc_c6aa82f7, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d108a090, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2],
+ InstrItinData <tc_c6ce9b3f, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_c6ebf8dd, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d1b5a4b6, /*tc_1*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ InstrItinData <tc_c74f796f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d2609065, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3, 2],
- [Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_d267fa19, /*tc_2early*/
- [InstrStage<1, [SLOT2]>], [],
- []>,
+ InstrItinData <tc_c82dc1ff, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [1],
+ [Hex_FWD]>,
- InstrItinData <tc_d2a33af5, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_caaebcba, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d63b71d1, /*tc_2early*/
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_cd7374a0, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d6a805a8, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [2, 1],
+ InstrItinData <tc_cde8b071, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_d95f4e98, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_cf47a43f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_da79106e, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [1, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_cf59f215, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dbe218dd, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2],
+ InstrItinData <tc_d088982c, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_dcfee7ae, /*tc_newvjump*/
- [InstrStage<1, [SLOT0]>], [3, 2],
+ InstrItinData <tc_d1090e34, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e17ce9ad, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2],
+ InstrItinData <tc_d24b2d85, /*tc_latepredstaia*/
+ [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d580173f, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d6bf0472, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_d9709180, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2480a7f, /*tc_st*/
+ InstrItinData <tc_d9f95eef, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3],
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c08bb4, /*tc_3stall*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
+ InstrItinData <tc_daa058fa, /*tc_3stall*/
+ [InstrStage<1, [SLOT0]>], [1, 1],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_dbdffe3d, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e2c31426, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [],
- []>,
+ InstrItinData <tc_e0739b8c, /*tc_1*/
+ [InstrStage<1, [SLOT2]>], [2, 2],
+ [Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e578178f, /*tc_ld*/
- [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_e1e0a2dc, /*tc_3stall*/
+ [InstrStage<1, [SLOT2]>], [],
+ []>,
- InstrItinData <tc_e836c161, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
+ InstrItinData <tc_e1e99bfa, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_e8c7a357, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_e216a5db, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_eb07ef6f, /*tc_2early*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2],
+ InstrItinData <tc_e421e012, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_e6b38e01, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ecfaae86, /*tc_3*/
- [InstrStage<1, [SLOT2]>], [1],
+ InstrItinData <tc_e7624c08, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,
- InstrItinData <tc_ef0ebaaa, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [1, 2],
- [Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_e7d02c66, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_ef2676fd, /*tc_st*/
- [InstrStage<1, [SLOT0]>], [],
- []>,
+ InstrItinData <tc_e913dc32, /*tc_3x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f027ebe9, /*tc_ld*/
- [InstrStage<1, [SLOT0]>], [2],
+ InstrItinData <tc_e9c822f7, /*tc_2latepred*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4],
[Hex_FWD]>,
- InstrItinData <tc_f055fbb6, /*tc_3x*/
- [InstrStage<1, [SLOT3]>], [2, 1],
+ InstrItinData <tc_e9fae2d6, /*tc_1*/
+ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1240c08, /*tc_2*/
- [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
-
- InstrItinData <tc_f16d5b17, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2],
+ InstrItinData <tc_ef20db1c, /*tc_3x*/
+ [InstrStage<1, [SLOT3]>], [4, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f1aa2cdb, /*tc_4x*/
- [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
- [Hex_FWD, Hex_FWD, Hex_FWD]>,
+ InstrItinData <tc_ef52ed71, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f26aa619, /*tc_1*/
- [InstrStage<1, [SLOT0, SLOT1]>], [3],
- [Hex_FWD]>,
+ InstrItinData <tc_ef84f62f, /*tc_2*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_f4608adc, /*tc_3stall*/
- [InstrStage<1, [SLOT0]>], [1, 1],
+ InstrItinData <tc_f2704b9a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2],
+ [Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f3eaa14b, /*tc_4x*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
[Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_faab1248, /*tc_2*/
+ InstrItinData <tc_f47d212f, /*tc_ld*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f49e76f4, /*tc_2*/
[InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_fcee8723, /*tc_st*/
- [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
+ InstrItinData <tc_f4f43fb5, /*tc_ld*/
+ [InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
- InstrItinData <tc_feb4974b, /*tc_3stall*/
- [InstrStage<1, [SLOT3]>], [2, 2],
+ InstrItinData <tc_f7dd9c9f, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [1, 2, 3],
+ [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f86c328a, /*tc_st*/
+ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_f8eeed7a, /*tc_1*/
+ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
+ [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
+
+ InstrItinData <tc_fcab4871, /*tc_newvjump*/
+ [InstrStage<1, [SLOT0]>], [],
+ []>,
+
+ InstrItinData <tc_ff9ee76e, /*tc_st*/
+ [InstrStage<1, [SLOT0]>], [2, 3],
[Hex_FWD, Hex_FWD]>
];
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.h Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepITypes.h -----------------------------------------------===//
+//===- HexagonDepITypes.h -------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,6 +6,9 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
namespace llvm {
namespace HexagonII {
@@ -15,8 +18,17 @@ enum Type {
TypeALU32_ADDI = 2,
TypeALU64 = 3,
TypeCJ = 4,
+ TypeCOPROC_VX = 5,
TypeCR = 6,
+ TypeCVI_4SLOT_MPY = 7,
+ TypeCVI_GATHER = 8,
+ TypeCVI_GATHER_RST = 9,
TypeCVI_HIST = 10,
+ TypeCVI_SCATTER = 11,
+ TypeCVI_SCATTER_DV = 12,
+ TypeCVI_SCATTER_NEW_RST = 13,
+ TypeCVI_SCATTER_NEW_ST = 14,
+ TypeCVI_SCATTER_RST = 15,
TypeCVI_VA = 16,
TypeCVI_VA_DV = 17,
TypeCVI_VINLANESAT = 18,
@@ -29,6 +41,7 @@ enum Type {
TypeCVI_VP = 25,
TypeCVI_VP_VS = 26,
TypeCVI_VS = 27,
+ TypeCVI_VS_VX = 28,
TypeCVI_VX = 29,
TypeCVI_VX_DV = 30,
TypeCVI_VX_LATE = 31,
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepITypes.td Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepITypes.td ----------------------------------------------===//
+//===- HexagonDepITypes.td ------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,6 +6,9 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
class IType<bits<6> t> { bits<6> Value = t; }
def TypeALU32_2op : IType<0>;
@@ -13,8 +16,17 @@ def TypeALU32_3op : IType<1>;
def TypeALU32_ADDI : IType<2>;
def TypeALU64 : IType<3>;
def TypeCJ : IType<4>;
+def TypeCOPROC_VX : IType<5>;
def TypeCR : IType<6>;
+def TypeCVI_4SLOT_MPY : IType<7>;
+def TypeCVI_GATHER : IType<8>;
+def TypeCVI_GATHER_RST : IType<9>;
def TypeCVI_HIST : IType<10>;
+def TypeCVI_SCATTER : IType<11>;
+def TypeCVI_SCATTER_DV : IType<12>;
+def TypeCVI_SCATTER_NEW_RST : IType<13>;
+def TypeCVI_SCATTER_NEW_ST : IType<14>;
+def TypeCVI_SCATTER_RST : IType<15>;
def TypeCVI_VA : IType<16>;
def TypeCVI_VA_DV : IType<17>;
def TypeCVI_VINLANESAT : IType<18>;
@@ -27,6 +39,7 @@ def TypeCVI_VM_VP_LDU : IType<24>;
def TypeCVI_VP : IType<25>;
def TypeCVI_VP_VS : IType<26>;
def TypeCVI_VS : IType<27>;
+def TypeCVI_VS_VX : IType<28>;
def TypeCVI_VX : IType<29>;
def TypeCVI_VX_DV : IType<30>;
def TypeCVI_VX_LATE : IType<31>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td?rev=320404&r1=320403&r2=320404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td Mon Dec 11 10:57:54 2017
@@ -1,4 +1,4 @@
-//===--- HexagonDepInstrFormats.td ----------------------------------------===//
+//===- HexagonDepInstrFormats.td ------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,6 +6,9 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// Automatically generated file, please consult code owner before editing.
+//===----------------------------------------------------------------------===//
+
class Enc_890909 : OpcodeHexagon {
bits <5> Rs32;
@@ -15,6 +18,18 @@ class Enc_890909 : OpcodeHexagon {
bits <2> Pe4;
let Inst{6-5} = Pe4{1-0};
}
+class Enc_9be1de : OpcodeHexagon {
+ bits <2> Qs4;
+ let Inst{6-5} = Qs4{1-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vw32;
+ let Inst{4-0} = Vw32{4-0};
+}
class Enc_527412 : OpcodeHexagon {
bits <2> Ps4;
let Inst{17-16} = Ps4{1-0};
@@ -46,14 +61,23 @@ class Enc_27b757 : OpcodeHexagon {
bits <5> Vs32;
let Inst{4-0} = Vs32{4-0};
}
-class Enc_5de85f : OpcodeHexagon {
+class Enc_8d04c3 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
+class Enc_1de724 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
let Inst{7-1} = Ii{8-2};
- bits <5> Rt32;
- let Inst{12-8} = Rt32{4-0};
- bits <3> Ns8;
- let Inst{18-16} = Ns8{2-0};
+ bits <4> Rs16;
+ let Inst{19-16} = Rs16{3-0};
+ bits <4> n1;
+ let Inst{28-28} = n1{3-3};
+ let Inst{24-22} = n1{2-0};
}
class Enc_0e41fa : OpcodeHexagon {
bits <5> Vuu32;
@@ -63,12 +87,48 @@ class Enc_0e41fa : OpcodeHexagon {
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
}
+class Enc_2a736a : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_3d6d37 : OpcodeHexagon {
+ bits <2> Qs4;
+ let Inst{6-5} = Qs4{1-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <5> Vw32;
+ let Inst{4-0} = Vw32{4-0};
+}
+class Enc_a641d0 : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <5> Vw32;
+ let Inst{4-0} = Vw32{4-0};
+}
class Enc_802dc0 : OpcodeHexagon {
bits <1> Ii;
let Inst{8-8} = Ii{0-0};
bits <2> Qv4;
let Inst{23-22} = Qv4{1-0};
}
+class Enc_6a4549 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_6b197f : OpcodeHexagon {
bits <4> Ii;
let Inst{8-5} = Ii{3-0};
@@ -77,6 +137,14 @@ class Enc_6b197f : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_1f3376 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vxx32;
+ let Inst{7-3} = Vxx32{4-0};
+}
class Enc_1f5d8f : OpcodeHexagon {
bits <1> Mu2;
let Inst{13-13} = Mu2{0-0};
@@ -165,6 +233,14 @@ class Enc_7eee72 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_310ba1 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vx32;
+ let Inst{4-0} = Vx32{4-0};
+}
class Enc_d7dc10 : OpcodeHexagon {
bits <5> Rs32;
let Inst{20-16} = Rs32{4-0};
@@ -191,6 +267,14 @@ class Enc_8dec2e : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_28dcbb : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vvv32;
+ let Inst{4-0} = Vvv32{4-0};
+}
class Enc_eaa9f8 : OpcodeHexagon {
bits <5> Vu32;
let Inst{12-8} = Vu32{4-0};
@@ -207,6 +291,14 @@ class Enc_509701 : OpcodeHexagon {
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
+class Enc_c84567 : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_830e5d : OpcodeHexagon {
bits <8> Ii;
let Inst{12-5} = Ii{7-0};
@@ -218,6 +310,12 @@ class Enc_830e5d : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_ae0040 : OpcodeHexagon {
+ bits <5> Rs32;
+ let Inst{20-16} = Rs32{4-0};
+ bits <6> Sd64;
+ let Inst{5-0} = Sd64{5-0};
+}
class Enc_79b8c8 : OpcodeHexagon {
bits <6> Ii;
let Inst{6-3} = Ii{5-2};
@@ -238,6 +336,16 @@ class Enc_58a8bf : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_e8ddd5 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Vss32;
+ let Inst{7-3} = Vss32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_041d7b : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -261,6 +369,14 @@ class Enc_f44229 : OpcodeHexagon {
bits <3> Nt8;
let Inst{10-8} = Nt8{2-0};
}
+class Enc_fc563d : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_aad80c : OpcodeHexagon {
bits <5> Vuu32;
let Inst{12-8} = Vuu32{4-0};
@@ -432,6 +548,13 @@ class Enc_6a5972 : OpcodeHexagon {
bits <4> Rt16;
let Inst{11-8} = Rt16{3-0};
}
+class Enc_ff3442 : OpcodeHexagon {
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+}
class Enc_53dca9 : OpcodeHexagon {
bits <6> Ii;
let Inst{11-8} = Ii{5-2};
@@ -456,6 +579,12 @@ class Enc_93af4c : OpcodeHexagon {
bits <4> Rx16;
let Inst{3-0} = Rx16{3-0};
}
+class Enc_621fba : OpcodeHexagon {
+ bits <5> Rs32;
+ let Inst{20-16} = Rs32{4-0};
+ bits <5> Gd32;
+ let Inst{4-0} = Gd32{4-0};
+}
class Enc_5bdd42 : OpcodeHexagon {
bits <7> Ii;
let Inst{8-5} = Ii{6-3};
@@ -464,6 +593,14 @@ class Enc_5bdd42 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_ad9bef : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vxx32;
+ let Inst{4-0} = Vxx32{4-0};
+}
class Enc_71f1b4 : OpcodeHexagon {
bits <6> Ii;
let Inst{8-5} = Ii{5-2};
@@ -483,6 +620,12 @@ class Enc_14640c : OpcodeHexagon {
let Inst{24-22} = n1{3-1};
let Inst{13-13} = n1{0-0};
}
+class Enc_2516bf : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_31db33 : OpcodeHexagon {
bits <2> Qt4;
let Inst{6-5} = Qt4{1-0};
@@ -513,6 +656,24 @@ class Enc_784502 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_9a9d62 : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Rt32;
+ let Inst{12-8} = Rt32{4-0};
+ bits <5> Vs32;
+ let Inst{7-3} = Vs32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
+class Enc_3a81ac : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_6413b6 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -592,6 +753,16 @@ class Enc_e39bb2 : OpcodeHexagon {
bits <4> Rd16;
let Inst{3-0} = Rd16{3-0};
}
+class Enc_7db2f8 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{13-9} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{8-4} = Vv32{4-0};
+ bits <4> Vdd16;
+ let Inst{3-0} = Vdd16{3-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_1b64fb : OpcodeHexagon {
bits <16> Ii;
let Inst{26-25} = Ii{15-14};
@@ -670,6 +841,10 @@ class Enc_fcf7a7 : OpcodeHexagon {
bits <2> Pd4;
let Inst{1-0} = Pd4{1-0};
}
+class Enc_2c3281 : OpcodeHexagon {
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_55355c : OpcodeHexagon {
bits <2> Ii;
let Inst{13-13} = Ii{1-1};
@@ -745,6 +920,10 @@ class Enc_fef969 : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_b2ffce : OpcodeHexagon {
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_63eaeb : OpcodeHexagon {
bits <2> Ii;
let Inst{1-0} = Ii{1-0};
@@ -769,6 +948,12 @@ class Enc_372c9d : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_9e9047 : OpcodeHexagon {
+ bits <2> Pt4;
+ let Inst{9-8} = Pt4{1-0};
+ bits <5> Rs32;
+ let Inst{20-16} = Rs32{4-0};
+}
class Enc_4dff07 : OpcodeHexagon {
bits <2> Qv4;
let Inst{12-11} = Qv4{1-0};
@@ -815,6 +1000,16 @@ class Enc_b388cf : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_880793 : OpcodeHexagon {
+ bits <3> Qt8;
+ let Inst{2-0} = Qt8{2-0};
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_ad1c74 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -854,6 +1049,16 @@ class Enc_5e87ce : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_158beb : OpcodeHexagon {
+ bits <2> Qs4;
+ let Inst{6-5} = Qs4{1-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vv32;
+ let Inst{4-0} = Vv32{4-0};
+}
class Enc_f7ea77 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -897,6 +1102,14 @@ class Enc_226535 : OpcodeHexagon {
bits <5> Rt32;
let Inst{4-0} = Rt32{4-0};
}
+class Enc_96f0fd : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+ bits <3> Qdd8;
+ let Inst{2-0} = Qdd8{2-0};
+}
class Enc_31aa6a : OpcodeHexagon {
bits <5> Ii;
let Inst{6-3} = Ii{4-1};
@@ -907,6 +1120,12 @@ class Enc_31aa6a : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_932b58 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+}
class Enc_397f23 : OpcodeHexagon {
bits <8> Ii;
let Inst{13-13} = Ii{7-7};
@@ -973,6 +1192,14 @@ class Enc_01d3d0 : OpcodeHexagon {
bits <5> Vdd32;
let Inst{4-0} = Vdd32{4-0};
}
+class Enc_3126d7 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_b0e9d8 : OpcodeHexagon {
bits <10> Ii;
let Inst{21-21} = Ii{9-9};
@@ -1049,6 +1276,12 @@ class Enc_88c16c : OpcodeHexagon {
bits <5> Rxx32;
let Inst{4-0} = Rxx32{4-0};
}
+class Enc_e7408c : OpcodeHexagon {
+ bits <6> Sss64;
+ let Inst{21-16} = Sss64{5-0};
+ bits <5> Rdd32;
+ let Inst{4-0} = Rdd32{4-0};
+}
class Enc_770858 : OpcodeHexagon {
bits <2> Ps4;
let Inst{6-5} = Ps4{1-0};
@@ -1090,6 +1323,16 @@ class Enc_412ff0 : OpcodeHexagon {
bits <5> Rxx32;
let Inst{12-8} = Rxx32{4-0};
}
+class Enc_8e9fbd : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+ bits <5> Vy32;
+ let Inst{12-8} = Vy32{4-0};
+}
class Enc_c9a18e : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -1134,6 +1377,16 @@ class Enc_d6990d : OpcodeHexagon {
bits <5> Vxx32;
let Inst{4-0} = Vxx32{4-0};
}
+class Enc_6c4697 : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Rt32;
+ let Inst{12-8} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_6c9440 : OpcodeHexagon {
bits <10> Ii;
let Inst{21-21} = Ii{9-9};
@@ -1278,6 +1531,12 @@ class Enc_a803e0 : OpcodeHexagon {
bits <5> Rs32;
let Inst{20-16} = Rs32{4-0};
}
+class Enc_fde0e3 : OpcodeHexagon {
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_45364e : OpcodeHexagon {
bits <5> Vu32;
let Inst{12-8} = Vu32{4-0};
@@ -1298,6 +1557,12 @@ class Enc_b909d2 : OpcodeHexagon {
let Inst{13-13} = n1{1-1};
let Inst{8-8} = n1{0-0};
}
+class Enc_790d6e : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_e6c957 : OpcodeHexagon {
bits <10> Ii;
let Inst{21-21} = Ii{9-9};
@@ -1358,6 +1623,14 @@ class Enc_0ed752 : OpcodeHexagon {
bits <5> Cdd32;
let Inst{4-0} = Cdd32{4-0};
}
+class Enc_908985 : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vss32;
+ let Inst{7-3} = Vss32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_143445 : OpcodeHexagon {
bits <13> Ii;
let Inst{26-25} = Ii{12-11};
@@ -1385,6 +1658,16 @@ class Enc_3e3989 : OpcodeHexagon {
let Inst{25-22} = n1{4-1};
let Inst{8-8} = n1{0-0};
}
+class Enc_12dd8f : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+}
class Enc_152467 : OpcodeHexagon {
bits <5> Ii;
let Inst{8-5} = Ii{4-1};
@@ -1393,6 +1676,14 @@ class Enc_152467 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_6b1bc4 : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <3> Qt8;
+ let Inst{10-8} = Qt8{2-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_daea09 : OpcodeHexagon {
bits <17> Ii;
let Inst{23-22} = Ii{16-15};
@@ -1421,6 +1712,32 @@ class Enc_a198f6 : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_a265b7 : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
+class Enc_4e4a80 : OpcodeHexagon {
+ bits <2> Qs4;
+ let Inst{6-5} = Qs4{1-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vvv32;
+ let Inst{4-0} = Vvv32{4-0};
+}
+class Enc_8d5d98 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vxx32;
+ let Inst{7-3} = Vxx32{4-0};
+}
class Enc_3dac0b : OpcodeHexagon {
bits <2> Qt4;
let Inst{6-5} = Qt4{1-0};
@@ -1463,6 +1780,16 @@ class Enc_2df31d : OpcodeHexagon {
bits <4> Rd16;
let Inst{3-0} = Rd16{3-0};
}
+class Enc_b0e553 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_25bef0 : OpcodeHexagon {
bits <16> Ii;
let Inst{26-25} = Ii{15-14};
@@ -1482,6 +1809,12 @@ class Enc_f82302 : OpcodeHexagon {
let Inst{26-25} = n1{2-1};
let Inst{23-23} = n1{0-0};
}
+class Enc_44271f : OpcodeHexagon {
+ bits <5> Gs32;
+ let Inst{20-16} = Gs32{4-0};
+ bits <5> Rd32;
+ let Inst{4-0} = Rd32{4-0};
+}
class Enc_83ee64 : OpcodeHexagon {
bits <5> Ii;
let Inst{12-8} = Ii{4-0};
@@ -1524,6 +1857,14 @@ class Enc_4df4e9 : OpcodeHexagon {
bits <3> Nt8;
let Inst{10-8} = Nt8{2-0};
}
+class Enc_263841 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vd32;
+ let Inst{4-0} = Vd32{4-0};
+}
class Enc_91b9fe : OpcodeHexagon {
bits <5> Ii;
let Inst{6-3} = Ii{4-1};
@@ -1564,6 +1905,11 @@ class Enc_bd1cbc : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_d0fe02 : OpcodeHexagon {
+ bits <5> Rxx32;
+ let Inst{20-16} = Rxx32{4-0};
+ bits <0> sgp10;
+}
class Enc_a30110 : OpcodeHexagon {
bits <5> Vu32;
let Inst{12-8} = Vu32{4-0};
@@ -1583,6 +1929,16 @@ class Enc_f3f408 : OpcodeHexagon {
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
}
+class Enc_ce4c54 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_690862 : OpcodeHexagon {
bits <13> Ii;
let Inst{26-25} = Ii{12-11};
@@ -1593,6 +1949,20 @@ class Enc_690862 : OpcodeHexagon {
bits <3> Nt8;
let Inst{10-8} = Nt8{2-0};
}
+class Enc_e570b0 : OpcodeHexagon {
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_3c46e8 : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{12-8} = Vuu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_2a3787 : OpcodeHexagon {
bits <13> Ii;
let Inst{26-25} = Ii{12-11};
@@ -1640,6 +2010,22 @@ class Enc_729ff7 : OpcodeHexagon {
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
+class Enc_5883d0 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_ff0e49 : OpcodeHexagon {
+ bits <5> Rss32;
+ let Inst{20-16} = Rss32{4-0};
+ bits <6> Sdd64;
+ let Inst{5-0} = Sdd64{5-0};
+}
class Enc_217147 : OpcodeHexagon {
bits <2> Qv4;
let Inst{23-22} = Qv4{1-0};
@@ -1674,6 +2060,14 @@ class Enc_541f26 : OpcodeHexagon {
bits <5> Rt32;
let Inst{12-8} = Rt32{4-0};
}
+class Enc_9aae4a : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+ bits <3> Qd8;
+ let Inst{2-0} = Qd8{2-0};
+}
class Enc_724154 : OpcodeHexagon {
bits <6> II;
let Inst{5-0} = II{5-0};
@@ -1781,6 +2175,12 @@ class Enc_22c845 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_ed5027 : OpcodeHexagon {
+ bits <5> Rss32;
+ let Inst{20-16} = Rss32{4-0};
+ bits <5> Gdd32;
+ let Inst{4-0} = Gdd32{4-0};
+}
class Enc_9b0bc1 : OpcodeHexagon {
bits <2> Pu4;
let Inst{6-5} = Pu4{1-0};
@@ -1828,6 +2228,12 @@ class Enc_96ce4f : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_2bbae6 : OpcodeHexagon {
+ bits <6> Ss64;
+ let Inst{21-16} = Ss64{5-0};
+ bits <5> Rd32;
+ let Inst{4-0} = Rd32{4-0};
+}
class Enc_143a3c : OpcodeHexagon {
bits <6> Ii;
let Inst{13-8} = Ii{5-0};
@@ -1959,6 +2365,26 @@ class Enc_b43b67 : OpcodeHexagon {
bits <2> Qx4;
let Inst{6-5} = Qx4{1-0};
}
+class Enc_1cd70f : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
+class Enc_3a527f : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Vs32;
+ let Inst{7-3} = Vs32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_4aca3a : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -1977,6 +2403,12 @@ class Enc_b38ffc : OpcodeHexagon {
bits <4> Rt16;
let Inst{3-0} = Rt16{3-0};
}
+class Enc_5c3a80 : OpcodeHexagon {
+ bits <3> Qt8;
+ let Inst{10-8} = Qt8{2-0};
+ bits <3> Qd8;
+ let Inst{5-3} = Qd8{2-0};
+}
class Enc_cda00a : OpcodeHexagon {
bits <12> Ii;
let Inst{19-16} = Ii{11-8};
@@ -1994,6 +2426,24 @@ class Enc_2fbf3c : OpcodeHexagon {
bits <4> Rd16;
let Inst{3-0} = Rd16{3-0};
}
+class Enc_a4ae28 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <3> Qd8;
+ let Inst{5-3} = Qd8{2-0};
+}
+class Enc_dd5f9f : OpcodeHexagon {
+ bits <3> Qtt8;
+ let Inst{2-0} = Qtt8{2-0};
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_70b24b : OpcodeHexagon {
bits <6> Ii;
let Inst{8-5} = Ii{5-2};
@@ -2040,6 +2490,16 @@ class Enc_08d755 : OpcodeHexagon {
bits <2> Pd4;
let Inst{1-0} = Pd4{1-0};
}
+class Enc_a7ca29 : OpcodeHexagon {
+ bits <3> Qt8;
+ let Inst{2-0} = Qt8{2-0};
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_1178da : OpcodeHexagon {
bits <3> Ii;
let Inst{7-5} = Ii{2-0};
@@ -2058,6 +2518,14 @@ class Enc_8dbe85 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_17a474 : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vs32;
+ let Inst{7-3} = Vs32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_5a18b3 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -2118,6 +2586,14 @@ class Enc_12b6e9 : OpcodeHexagon {
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
+class Enc_9a895f : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_6f70ca : OpcodeHexagon {
bits <8> Ii;
let Inst{8-4} = Ii{7-3};
@@ -2130,6 +2606,12 @@ class Enc_7222b7 : OpcodeHexagon {
}
class Enc_e3b0c4 : OpcodeHexagon {
}
+class Enc_d7e8ba : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_a255dc : OpcodeHexagon {
bits <3> Ii;
let Inst{10-8} = Ii{2-0};
@@ -2138,6 +2620,24 @@ class Enc_a255dc : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_cb785b : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vdd32;
+ let Inst{4-0} = Vdd32{4-0};
+}
+class Enc_5b76ab : OpcodeHexagon {
+ bits <10> Ii;
+ let Inst{21-21} = Ii{9-9};
+ let Inst{13-8} = Ii{8-3};
+ let Inst{2-0} = Ii{2-0};
+ bits <5> Vs32;
+ let Inst{7-3} = Vs32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_cb4b4e : OpcodeHexagon {
bits <2> Pu4;
let Inst{6-5} = Pu4{1-0};
@@ -2148,6 +2648,24 @@ class Enc_cb4b4e : OpcodeHexagon {
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
+class Enc_fbacc2 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vxx32;
+ let Inst{7-3} = Vxx32{4-0};
+ bits <5> Vy32;
+ let Inst{12-8} = Vy32{4-0};
+}
+class Enc_2ad23d : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+}
class Enc_9cdba7 : OpcodeHexagon {
bits <8> Ii;
let Inst{12-5} = Ii{7-0};
@@ -2165,6 +2683,10 @@ class Enc_5cd7e9 : OpcodeHexagon {
bits <5> Ryy32;
let Inst{4-0} = Ryy32{4-0};
}
+class Enc_e7c9de : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+}
class Enc_454a26 : OpcodeHexagon {
bits <2> Pt4;
let Inst{9-8} = Pt4{1-0};
@@ -2193,6 +2715,16 @@ class Enc_c175d0 : OpcodeHexagon {
bits <4> Rd16;
let Inst{3-0} = Rd16{3-0};
}
+class Enc_16c48b : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <5> Vw32;
+ let Inst{4-0} = Vw32{4-0};
+}
class Enc_895bd9 : OpcodeHexagon {
bits <2> Qu4;
let Inst{9-8} = Qu4{1-0};
@@ -2254,6 +2786,14 @@ class Enc_d2c7f1 : OpcodeHexagon {
bits <2> Pe4;
let Inst{6-5} = Pe4{1-0};
}
+class Enc_dcfcbb : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_3680c2 : OpcodeHexagon {
bits <7> Ii;
let Inst{11-5} = Ii{6-0};
@@ -2282,6 +2822,32 @@ class Enc_e957fb : OpcodeHexagon {
bits <5> Rt32;
let Inst{12-8} = Rt32{4-0};
}
+class Enc_2146c1 : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <3> Qss8;
+ let Inst{2-0} = Qss8{2-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
+class Enc_a662ae : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_8f7cc3 : OpcodeHexagon {
+ bits <3> Qtt8;
+ let Inst{10-8} = Qtt8{2-0};
+ bits <3> Qdd8;
+ let Inst{5-3} = Qdd8{2-0};
+}
class Enc_c9e3bc : OpcodeHexagon {
bits <4> Ii;
let Inst{13-13} = Ii{3-3};
@@ -2314,6 +2880,40 @@ class Enc_0b2e5b : OpcodeHexagon {
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
}
+class Enc_6f83e7 : OpcodeHexagon {
+ bits <2> Qv4;
+ let Inst{23-22} = Qv4{1-0};
+ bits <5> Vd32;
+ let Inst{4-0} = Vd32{4-0};
+}
+class Enc_46f33d : OpcodeHexagon {
+ bits <5> Rss32;
+ let Inst{20-16} = Rss32{4-0};
+ bits <5> Rt32;
+ let Inst{12-8} = Rt32{4-0};
+}
+class Enc_c1652e : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <3> Qd8;
+ let Inst{5-3} = Qd8{2-0};
+}
+class Enc_b5b643 : OpcodeHexagon {
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+}
+class Enc_85daf5 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+}
class Enc_d483b9 : OpcodeHexagon {
bits <1> Ii;
let Inst{5-5} = Ii{0-0};
@@ -2346,6 +2946,26 @@ class Enc_70fb07 : OpcodeHexagon {
bits <5> Rxx32;
let Inst{4-0} = Rxx32{4-0};
}
+class Enc_6c9ee0 : OpcodeHexagon {
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
+class Enc_72a92d : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{12-8} = Vuu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vxx32;
+ let Inst{7-3} = Vxx32{4-0};
+}
+class Enc_44661f : OpcodeHexagon {
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_277737 : OpcodeHexagon {
bits <8> Ii;
let Inst{22-21} = Ii{7-6};
@@ -2496,6 +3116,14 @@ class Enc_8e583a : OpcodeHexagon {
let Inst{25-23} = n1{3-1};
let Inst{13-13} = n1{0-0};
}
+class Enc_334c2b : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{12-8} = Vuu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_b886fd : OpcodeHexagon {
bits <5> Ii;
let Inst{6-3} = Ii{4-1};
@@ -2549,12 +3177,36 @@ class Enc_8dbdfe : OpcodeHexagon {
bits <3> Nt8;
let Inst{10-8} = Nt8{2-0};
}
+class Enc_7dc746 : OpcodeHexagon {
+ bits <3> Quu8;
+ let Inst{10-8} = Quu8{2-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <3> Qdd8;
+ let Inst{5-3} = Qdd8{2-0};
+}
class Enc_90cd8b : OpcodeHexagon {
bits <5> Rss32;
let Inst{20-16} = Rss32{4-0};
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_b8513b : OpcodeHexagon {
+ bits <5> Vuu32;
+ let Inst{20-16} = Vuu32{4-0};
+ bits <5> Vvv32;
+ let Inst{12-8} = Vvv32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
+class Enc_b3bac4 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rtt32;
+ let Inst{20-16} = Rtt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+}
class Enc_bd0b33 : OpcodeHexagon {
bits <10> Ii;
let Inst{21-21} = Ii{9-9};
@@ -2564,6 +3216,24 @@ class Enc_bd0b33 : OpcodeHexagon {
bits <2> Pd4;
let Inst{1-0} = Pd4{1-0};
}
+class Enc_843e80 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vd32;
+ let Inst{7-3} = Vd32{4-0};
+ bits <3> Qxx8;
+ let Inst{2-0} = Qxx8{2-0};
+}
+class Enc_8b8927 : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <1> Mu2;
+ let Inst{13-13} = Mu2{0-0};
+ bits <5> Vv32;
+ let Inst{4-0} = Vv32{4-0};
+}
class Enc_c7cd90 : OpcodeHexagon {
bits <4> Ii;
let Inst{6-3} = Ii{3-0};
@@ -2711,15 +3381,24 @@ class Enc_1a9974 : OpcodeHexagon {
bits <5> Rtt32;
let Inst{4-0} = Rtt32{4-0};
}
-class Enc_1de724 : OpcodeHexagon {
+class Enc_9ce456 : OpcodeHexagon {
+ bits <10> Ii;
+ let Inst{21-21} = Ii{9-9};
+ let Inst{13-8} = Ii{8-3};
+ let Inst{2-0} = Ii{2-0};
+ bits <5> Vss32;
+ let Inst{7-3} = Vss32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
+class Enc_5de85f : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
let Inst{7-1} = Ii{8-2};
- bits <4> Rs16;
- let Inst{19-16} = Rs16{3-0};
- bits <4> n1;
- let Inst{28-28} = n1{3-3};
- let Inst{24-22} = n1{2-0};
+ bits <5> Rt32;
+ let Inst{12-8} = Rt32{4-0};
+ bits <3> Ns8;
+ let Inst{18-16} = Ns8{2-0};
}
class Enc_dd766a : OpcodeHexagon {
bits <5> Vu32;
@@ -2737,6 +3416,14 @@ class Enc_0b51ce : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_b5e54d : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rs32;
+ let Inst{20-16} = Rs32{4-0};
+ bits <5> Rdd32;
+ let Inst{4-0} = Rdd32{4-0};
+}
class Enc_b4e6cf : OpcodeHexagon {
bits <10> Ii;
let Inst{21-21} = Ii{9-9};
@@ -2755,6 +3442,12 @@ class Enc_44215c : OpcodeHexagon {
bits <3> Nt8;
let Inst{10-8} = Nt8{2-0};
}
+class Enc_0aa344 : OpcodeHexagon {
+ bits <5> Gss32;
+ let Inst{20-16} = Gss32{4-0};
+ bits <5> Rdd32;
+ let Inst{4-0} = Rdd32{4-0};
+}
class Enc_a21d47 : OpcodeHexagon {
bits <6> Ii;
let Inst{10-5} = Ii{5-0};
@@ -2786,6 +3479,16 @@ class Enc_645d54 : OpcodeHexagon {
bits <5> Rdd32;
let Inst{4-0} = Rdd32{4-0};
}
+class Enc_b5d5a7 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vs32;
+ let Inst{7-3} = Vs32{4-0};
+}
class Enc_667b39 : OpcodeHexagon {
bits <5> Css32;
let Inst{20-16} = Css32{4-0};
@@ -2843,6 +3546,16 @@ class Enc_b8c967 : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_f106e0 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{8-4} = Vv32{4-0};
+ bits <5> Vt32;
+ let Inst{13-9} = Vt32{4-0};
+ bits <4> Vdd16;
+ let Inst{3-0} = Vdd16{3-0};
+}
class Enc_fb6577 : OpcodeHexagon {
bits <2> Pu4;
let Inst{9-8} = Pu4{1-0};
@@ -2851,6 +3564,20 @@ class Enc_fb6577 : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_37c406 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vv32;
+ let Inst{12-8} = Vv32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <4> Vdd16;
+ let Inst{7-4} = Vdd16{3-0};
+}
+class Enc_403871 : OpcodeHexagon {
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_2bae10 : OpcodeHexagon {
bits <4> Ii;
let Inst{10-8} = Ii{3-1};
@@ -2859,6 +3586,22 @@ class Enc_2bae10 : OpcodeHexagon {
bits <4> Rd16;
let Inst{3-0} = Rd16{3-0};
}
+class Enc_f3adb6 : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
+class Enc_aac08c : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+}
class Enc_c4dc92 : OpcodeHexagon {
bits <2> Qv4;
let Inst{23-22} = Qv4{1-0};
@@ -3000,6 +3743,13 @@ class Enc_134437 : OpcodeHexagon {
bits <2> Qd4;
let Inst{1-0} = Qd4{1-0};
}
+class Enc_33f8ba : OpcodeHexagon {
+ bits <8> Ii;
+ let Inst{12-8} = Ii{7-3};
+ let Inst{4-2} = Ii{2-0};
+ bits <5> Rx32;
+ let Inst{20-16} = Rx32{4-0};
+}
class Enc_97d666 : OpcodeHexagon {
bits <4> Rs16;
let Inst{7-4} = Rs16{3-0};
@@ -3016,6 +3766,16 @@ class Enc_f82eaf : OpcodeHexagon {
bits <5> Rd32;
let Inst{4-0} = Rd32{4-0};
}
+class Enc_57e245 : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+ bits <5> Vy32;
+ let Inst{12-8} = Vy32{4-0};
+}
class Enc_69d63b : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
@@ -3082,6 +3842,24 @@ class Enc_7eaeb6 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
+class Enc_274a4c : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{20-16} = Vu32{4-0};
+ bits <3> Rt8;
+ let Inst{2-0} = Rt8{2-0};
+ bits <5> Vx32;
+ let Inst{7-3} = Vx32{4-0};
+ bits <5> Vy32;
+ let Inst{12-8} = Vy32{4-0};
+}
+class Enc_aceeef : OpcodeHexagon {
+ bits <5> Vu32;
+ let Inst{12-8} = Vu32{4-0};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_f55a0c : OpcodeHexagon {
bits <6> Ii;
let Inst{11-8} = Ii{5-2};
@@ -3120,6 +3898,16 @@ class Enc_7b523d : OpcodeHexagon {
bits <5> Vxx32;
let Inst{4-0} = Vxx32{4-0};
}
+class Enc_c39a8b : OpcodeHexagon {
+ bits <16> Ii;
+ let Inst{21-21} = Ii{15-15};
+ let Inst{13-8} = Ii{14-9};
+ let Inst{2-0} = Ii{8-6};
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vss32;
+ let Inst{7-3} = Vss32{4-0};
+}
class Enc_47ef61 : OpcodeHexagon {
bits <3> Ii;
let Inst{7-5} = Ii{2-0};
@@ -3229,6 +4017,16 @@ class Enc_eca7c8 : OpcodeHexagon {
bits <5> Rt32;
let Inst{4-0} = Rt32{4-0};
}
+class Enc_598f6c : OpcodeHexagon {
+ bits <5> Rtt32;
+ let Inst{12-8} = Rtt32{4-0};
+}
+class Enc_41dcc3 : OpcodeHexagon {
+ bits <5> Rt32;
+ let Inst{20-16} = Rt32{4-0};
+ bits <5> Vdd32;
+ let Inst{7-3} = Vdd32{4-0};
+}
class Enc_4b39e4 : OpcodeHexagon {
bits <3> Ii;
let Inst{7-5} = Ii{2-0};
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