[PATCH] D40067: [X86] Update BTVER2 sched numbers for some AVX instructions (xmm version)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:582
+}
+def : InstRW<[WriteVMULPSLd], (instregex "VMULPSrm", "VMULSSrm")>;
+
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The MULPS versions don't seem to be necessary - they match the WriteFMul defaults - its just the MULPD versions we need.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:610
+}
+def : InstRW<[WriteVMOVTPSt], (instregex "VMOVNTP(S|D)mr")>;
+
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Please can you add the SSE4A MOVNTSDmr/MOVNTSSmr cases here? Note they don't have a V prefix.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:619
+
+def WriteVecMove: SchedWriteRes<[JFPU01]> {}
+def WriteVecStore: SchedWriteRes<[JFPU01, JSAGU]> {}
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Are the moves doing anything at all? I didn't see any changes to the schedule tests. If not just remove this


https://reviews.llvm.org/D40067