[llvm] r320389 - Normalize line endings. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 09:01:21 PST 2017
Author: rksimon
Date: Mon Dec 11 09:01:21 2017
New Revision: 320389
URL: http://llvm.org/viewvc/llvm-project?rev=320389&view=rev
Log:
Normalize line endings. NFCI.
Modified:
llvm/trunk/lib/Target/X86/X86InstrExtension.td
Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=320389&r1=320388&r2=320389&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Mon Dec 11 09:01:21 2017
@@ -9,36 +9,36 @@
//
// This file describes the sign and zero extension operations.
//
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0 in {
- let Defs = [AX], Uses = [AL] in // AX = signext(AL)
- def CBW : I<0x98, RawFrm, (outs), (ins),
- "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
- let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
- def CWDE : I<0x98, RawFrm, (outs), (ins),
- "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
-
- let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
- def CWD : I<0x99, RawFrm, (outs), (ins),
- "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
- let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
- def CDQ : I<0x99, RawFrm, (outs), (ins),
- "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
-
-
- let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
- def CDQE : RI<0x98, RawFrm, (outs), (ins),
- "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
-
- let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
- def CQO : RI<0x99, RawFrm, (outs), (ins),
- "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
-}
-
-// Sign/Zero extenders
-let hasSideEffects = 0 in {
-def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0 in {
+ let Defs = [AX], Uses = [AL] in // AX = signext(AL)
+ def CBW : I<0x98, RawFrm, (outs), (ins),
+ "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+ let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
+ def CWDE : I<0x98, RawFrm, (outs), (ins),
+ "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+ let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
+ def CWD : I<0x99, RawFrm, (outs), (ins),
+ "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+ let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
+ def CDQ : I<0x99, RawFrm, (outs), (ins),
+ "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+
+ let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
+ def CDQE : RI<0x98, RawFrm, (outs), (ins),
+ "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
+
+ let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
+ def CQO : RI<0x99, RawFrm, (outs), (ins),
+ "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
+}
+
+// Sign/Zero extenders
+let hasSideEffects = 0 in {
+def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
TB, OpSize16, Sched<[WriteALU]>;
let mayLoad = 1 in
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