[PATCH] D41071: [RISCV] implemented assembler pseudo floating point instructions

[Mario Werner via Phabricator via llvm-commits]

niosHD created this revision.
Herald added subscribers: sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar.

Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon https://reviews.llvm.org/D40902.


https://reviews.llvm.org/D41071

Files:
  lib/Target/RISCV/RISCVInstrInfoD.td
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/MC/RISCV/rvd-aliases-valid.s
  test/MC/RISCV/rvf-aliases-valid.s

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