[llvm] r320375 - [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 07:23:20 PST 2017
Author: dpreobra
Date: Mon Dec 11 07:23:20 2017
New Revision: 320375
URL: http://llvm.org/viewvc/llvm-project?rev=320375&view=rev
Log:
[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559
Reviewers: vpykhtin, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41007
Added:
llvm/trunk/test/MC/Disassembler/AMDGPU/trap_gfx9.txt
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/SIDefines.h
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/trunk/test/MC/AMDGPU/literalv216-err.s
llvm/trunk/test/MC/AMDGPU/trap.s
llvm/trunk/test/MC/AMDGPU/vop1-gfx9-err.s
llvm/trunk/test/MC/AMDGPU/vop_sdwa.s
llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Dec 11 07:23:20 2017
@@ -2578,6 +2578,25 @@ bool AMDGPUAsmParser::ParseDirective(Asm
bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
unsigned RegNo) const {
+
+ for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true);
+ R.isValid(); ++R) {
+ if (*R == RegNo)
+ return isGFX9();
+ }
+
+ switch (RegNo) {
+ case AMDGPU::TBA:
+ case AMDGPU::TBA_LO:
+ case AMDGPU::TBA_HI:
+ case AMDGPU::TMA:
+ case AMDGPU::TMA_LO:
+ case AMDGPU::TMA_HI:
+ return !isGFX9();
+ default:
+ break;
+ }
+
if (isCI())
return true;
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Mon Dec 11 07:23:20 2017
@@ -250,7 +250,7 @@ DecodeStatus AMDGPUDisassembler::convert
int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
if (SDst != -1) {
// VOPC - insert VCC register as sdst
- insertNamedMCOperand(MI, MCOperand::createReg(AMDGPU::VCC),
+ insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
AMDGPU::OpName::sdst);
} else {
// VOP1/2 - insert omod if present in instruction
@@ -277,7 +277,7 @@ MCOperand AMDGPUDisassembler::errOperand
inline
MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
- return MCOperand::createReg(RegId);
+ return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
}
inline
@@ -571,6 +571,15 @@ unsigned AMDGPUDisassembler::getTtmpClas
}
}
+int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
+ using namespace AMDGPU::EncValues;
+
+ unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN;
+ unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX;
+
+ return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
+}
+
MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
using namespace AMDGPU::EncValues;
@@ -583,8 +592,10 @@ MCOperand AMDGPUDisassembler::decodeSrcO
assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
}
- if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
- return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
+
+ int TTmpIdx = getTTmpIdx(Val);
+ if (TTmpIdx >= 0) {
+ return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
}
if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
@@ -612,17 +623,17 @@ MCOperand AMDGPUDisassembler::decodeSpec
using namespace AMDGPU;
switch (Val) {
- case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
- case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
+ case 102: return createRegOperand(FLAT_SCR_LO);
+ case 103: return createRegOperand(FLAT_SCR_HI);
// ToDo: no support for xnack_mask_lo/_hi register
case 104:
case 105: break;
case 106: return createRegOperand(VCC_LO);
case 107: return createRegOperand(VCC_HI);
- case 108: return createRegOperand(TBA_LO);
- case 109: return createRegOperand(TBA_HI);
- case 110: return createRegOperand(TMA_LO);
- case 111: return createRegOperand(TMA_HI);
+ case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
+ case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);
+ case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);
+ case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);
case 124: return createRegOperand(M0);
case 126: return createRegOperand(EXEC_LO);
case 127: return createRegOperand(EXEC_HI);
@@ -645,10 +656,10 @@ MCOperand AMDGPUDisassembler::decodeSpec
using namespace AMDGPU;
switch (Val) {
- case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
+ case 102: return createRegOperand(FLAT_SCR);
case 106: return createRegOperand(VCC);
- case 108: return createRegOperand(TBA);
- case 110: return createRegOperand(TMA);
+ case 108: assert(!isGFX9()); return createRegOperand(TBA);
+ case 110: assert(!isGFX9()); return createRegOperand(TMA);
case 126: return createRegOperand(EXEC);
default: break;
}
@@ -672,6 +683,11 @@ MCOperand AMDGPUDisassembler::decodeSDWA
return createSRegOperand(getSgprClassId(Width),
Val - SDWA9EncValues::SRC_SGPR_MIN);
}
+ if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
+ Val <= SDWA9EncValues::SRC_TTMP_MAX) {
+ return createSRegOperand(getTtmpClassId(Width),
+ Val - SDWA9EncValues::SRC_TTMP_MIN);
+ }
return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN);
} else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
@@ -695,7 +711,11 @@ MCOperand AMDGPUDisassembler::decodeSDWA
"SDWAVopcDst should be present only on GFX9");
if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
- if (Val > AMDGPU::EncValues::SGPR_MAX) {
+
+ int TTmpIdx = getTTmpIdx(Val);
+ if (TTmpIdx >= 0) {
+ return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
+ } else if (Val > AMDGPU::EncValues::SGPR_MAX) {
return decodeSpecialReg64(Val);
} else {
return createSRegOperand(getSgprClassId(OPW64), Val);
@@ -705,6 +725,14 @@ MCOperand AMDGPUDisassembler::decodeSDWA
}
}
+bool AMDGPUDisassembler::isVI() const {
+ return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
+}
+
+bool AMDGPUDisassembler::isGFX9() const {
+ return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
+}
+
//===----------------------------------------------------------------------===//
// AMDGPUSymbolizer
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h Mon Dec 11 07:23:20 2017
@@ -111,7 +111,12 @@ public:
MCOperand decodeSDWASrc16(unsigned Val) const;
MCOperand decodeSDWASrc32(unsigned Val) const;
MCOperand decodeSDWAVopcDst(unsigned Val) const;
-};
+
+ int getTTmpIdx(unsigned Val) const;
+
+ bool isVI() const;
+ bool isGFX9() const;
+ };
//===----------------------------------------------------------------------===//
// AMDGPUSymbolizer
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Mon Dec 11 07:23:20 2017
@@ -344,16 +344,6 @@ void AMDGPUInstPrinter::printRegOperand(
} else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)) {
O << 's';
NumRegs = 16;
- } else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)) {
- O << "ttmp";
- NumRegs = 2;
- // Trap temps start at offset 112. TODO: Get this from tablegen.
- RegIdx -= 112;
- } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)) {
- O << "ttmp";
- NumRegs = 4;
- // Trap temps start at offset 112. TODO: Get this from tablegen.
- RegIdx -= 112;
} else {
O << getRegisterName(RegNo);
return;
Modified: llvm/trunk/lib/Target/AMDGPU/SIDefines.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIDefines.h?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIDefines.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h Mon Dec 11 07:23:20 2017
@@ -194,8 +194,10 @@ namespace EncValues { // Encoding values
enum {
SGPR_MIN = 0,
SGPR_MAX = 101,
- TTMP_MIN = 112,
- TTMP_MAX = 123,
+ TTMP_VI_MIN = 112,
+ TTMP_VI_MAX = 123,
+ TTMP_GFX9_MIN = 108,
+ TTMP_GFX9_MAX = 123,
INLINE_INTEGER_C_MIN = 128,
INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
INLINE_INTEGER_C_MAX = 208,
@@ -368,6 +370,8 @@ enum SDWA9EncValues{
SRC_VGPR_MAX = 255,
SRC_SGPR_MIN = 256,
SRC_SGPR_MAX = 357,
+ SRC_TTMP_MIN = 364,
+ SRC_TTMP_MAX = 379,
};
} // namespace SDWA
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Mon Dec 11 07:23:20 2017
@@ -172,6 +172,8 @@ BitVector SIRegisterInfo::getReservedReg
reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
+ reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
+ reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Mon Dec 11 07:23:20 2017
@@ -77,18 +77,11 @@ def TMA : RegisterWithSubRegs<"tma", [TM
let HWEncoding = 110;
}
-def TTMP0 : SIReg <"ttmp0", 112>;
-def TTMP1 : SIReg <"ttmp1", 113>;
-def TTMP2 : SIReg <"ttmp2", 114>;
-def TTMP3 : SIReg <"ttmp3", 115>;
-def TTMP4 : SIReg <"ttmp4", 116>;
-def TTMP5 : SIReg <"ttmp5", 117>;
-def TTMP6 : SIReg <"ttmp6", 118>;
-def TTMP7 : SIReg <"ttmp7", 119>;
-def TTMP8 : SIReg <"ttmp8", 120>;
-def TTMP9 : SIReg <"ttmp9", 121>;
-def TTMP10 : SIReg <"ttmp10", 122>;
-def TTMP11 : SIReg <"ttmp11", 123>;
+foreach Index = 0-15 in {
+ def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>;
+ def TTMP#Index#_gfx9 : SIReg<"ttmp"#Index, !add(108, Index)>;
+ def TTMP#Index : SIReg<"", 0>;
+}
multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
def _ci : SIReg<n, ci_e>;
@@ -192,7 +185,7 @@ def SGPR_512 : RegisterTuples<[sub0, sub
// Trap handler TMP 32-bit registers
def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
- (add (sequence "TTMP%u", 0, 11))> {
+ (add (sequence "TTMP%u", 0, 15))> {
let isAllocatable = 0;
}
@@ -208,6 +201,36 @@ def TTMP_128Regs : RegisterTuples<[sub0,
(add (decimate (shl TTMP_32, 2), 4)),
(add (decimate (shl TTMP_32, 3), 4))]>;
+class TmpRegTuples <string tgt,
+ bit Is64Bit,
+ int Index0,
+ int Index1 = !add(Index0, 1),
+ int Index2 = !add(Index0, !if(Is64Bit, 1, 2)),
+ int Index3 = !add(Index0, !if(Is64Bit, 1, 3)),
+ string name = "ttmp["#Index0#":"#Index3#"]",
+ Register r0 = !cast<Register>("TTMP"#Index0#tgt),
+ Register r1 = !cast<Register>("TTMP"#Index1#tgt),
+ Register r2 = !cast<Register>("TTMP"#Index2#tgt),
+ Register r3 = !cast<Register>("TTMP"#Index3#tgt)> :
+ RegisterWithSubRegs<name, !if(Is64Bit, [r0, r1], [r0, r1, r2, r3])> {
+ let SubRegIndices = !if(Is64Bit, [sub0, sub1], [sub0, sub1, sub2, sub3]);
+ let HWEncoding = r0.HWEncoding;
+}
+
+foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in {
+ def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 1, Index>;
+ def TTMP#Index#_TTMP#!add(Index,1)#_gfx9 : TmpRegTuples<"_gfx9", 1, Index>;
+}
+
+foreach Index = {0, 4, 8, 12} in {
+ def TTMP#Index#_TTMP#!add(Index,1)#
+ _TTMP#!add(Index,2)#
+ _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 0, Index>;
+ def TTMP#Index#_TTMP#!add(Index,1)#
+ _TTMP#!add(Index,2)#
+ _TTMP#!add(Index,3)#_gfx9 : TmpRegTuples<"_gfx9", 0, Index>;
+}
+
// VGPR 32-bit registers
// i16/f16 only on VI+
def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Mon Dec 11 07:23:20 2017
@@ -569,44 +569,68 @@ bool isRegIntersect(unsigned Reg0, unsig
return false;
}
-unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
-
- switch(Reg) {
- default: break;
- case AMDGPU::FLAT_SCR:
- assert(!isSI(STI));
- return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
-
- case AMDGPU::FLAT_SCR_LO:
- assert(!isSI(STI));
- return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
-
- case AMDGPU::FLAT_SCR_HI:
- assert(!isSI(STI));
- return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
+#define MAP_REG2REG \
+ using namespace AMDGPU; \
+ switch(Reg) { \
+ default: return Reg; \
+ CASE_CI_VI(FLAT_SCR) \
+ CASE_CI_VI(FLAT_SCR_LO) \
+ CASE_CI_VI(FLAT_SCR_HI) \
+ CASE_VI_GFX9(TTMP0) \
+ CASE_VI_GFX9(TTMP1) \
+ CASE_VI_GFX9(TTMP2) \
+ CASE_VI_GFX9(TTMP3) \
+ CASE_VI_GFX9(TTMP4) \
+ CASE_VI_GFX9(TTMP5) \
+ CASE_VI_GFX9(TTMP6) \
+ CASE_VI_GFX9(TTMP7) \
+ CASE_VI_GFX9(TTMP8) \
+ CASE_VI_GFX9(TTMP9) \
+ CASE_VI_GFX9(TTMP10) \
+ CASE_VI_GFX9(TTMP11) \
+ CASE_VI_GFX9(TTMP12) \
+ CASE_VI_GFX9(TTMP13) \
+ CASE_VI_GFX9(TTMP14) \
+ CASE_VI_GFX9(TTMP15) \
+ CASE_VI_GFX9(TTMP0_TTMP1) \
+ CASE_VI_GFX9(TTMP2_TTMP3) \
+ CASE_VI_GFX9(TTMP4_TTMP5) \
+ CASE_VI_GFX9(TTMP6_TTMP7) \
+ CASE_VI_GFX9(TTMP8_TTMP9) \
+ CASE_VI_GFX9(TTMP10_TTMP11) \
+ CASE_VI_GFX9(TTMP12_TTMP13) \
+ CASE_VI_GFX9(TTMP14_TTMP15) \
+ CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
+ CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
+ CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
+ CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
}
- return Reg;
+
+#define CASE_CI_VI(node) \
+ assert(!isSI(STI)); \
+ case node: return isCI(STI) ? node##_ci : node##_vi;
+
+#define CASE_VI_GFX9(node) \
+ case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
+
+unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
+ MAP_REG2REG
}
-unsigned mc2PseudoReg(unsigned Reg) {
- switch (Reg) {
- case AMDGPU::FLAT_SCR_ci:
- case AMDGPU::FLAT_SCR_vi:
- return FLAT_SCR;
-
- case AMDGPU::FLAT_SCR_LO_ci:
- case AMDGPU::FLAT_SCR_LO_vi:
- return AMDGPU::FLAT_SCR_LO;
-
- case AMDGPU::FLAT_SCR_HI_ci:
- case AMDGPU::FLAT_SCR_HI_vi:
- return AMDGPU::FLAT_SCR_HI;
+#undef CASE_CI_VI
+#undef CASE_VI_GFX9
- default:
- return Reg;
- }
+#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
+#define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
+
+unsigned mc2PseudoReg(unsigned Reg) {
+ MAP_REG2REG
}
+#undef CASE_CI_VI
+#undef CASE_VI_GFX9
+#undef MAP_REG2REG
+
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
assert(OpNo < Desc.NumOperands);
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
Modified: llvm/trunk/test/MC/AMDGPU/literalv216-err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/literalv216-err.s?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/literalv216-err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/literalv216-err.s Mon Dec 11 07:23:20 2017
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
v_pk_add_f16 v1, -17, v2
// GFX9: :19: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/AMDGPU/trap.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/trap.s?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/trap.s (original)
+++ llvm/trunk/test/MC/AMDGPU/trap.s Mon Dec 11 07:23:20 2017
@@ -1,6 +1,12 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOGFX9
//===----------------------------------------------------------------------===//
// Trap Handler related - 32 bit registers
@@ -9,90 +15,130 @@
s_add_u32 ttmp0, ttmp0, 4
// SICI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
// VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
+// GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
s_add_u32 ttmp4, 8, ttmp4
// SICI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
// VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
+// GXF9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
s_add_u32 ttmp4, ttmp4, 0x00000100
// SICI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
// VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
+// GXF9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
s_add_u32 ttmp4, ttmp4, 4
// SICI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
// VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
+// GXF9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
s_add_u32 ttmp4, ttmp8, ttmp4
// SICI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
// VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
+// GXF9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
s_and_b32 ttmp10, ttmp8, 0x00000080
// SICI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
// VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
+// GXF9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x74,0x86,0x80,0x00,0x00,0x00]
s_and_b32 ttmp9, tma_hi, 0x0000ffff
// SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
// VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
+// NOGFX9: error: not a valid operand
s_and_b32 ttmp9, ttmp9, 0x000001ff
// SICI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
// VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
+// GXF9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
s_and_b32 ttmp9, tma_lo, 0xffff0000
// SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
// VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
+// NOGFX9: error: not a valid operand
s_and_b32 ttmp9, ttmp9, ttmp8
// SICI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x87]
// VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
+// GXF9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x78,0x75,0x86]
s_and_b32 ttmp8, ttmp1, 0x01000000
// SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
// VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
+// GXF9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
s_cmp_eq_i32 ttmp8, 0
// SICI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
// VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
+// GXF9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
s_cmp_eq_i32 ttmp8, 0x000000fe
// SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
// VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
+// GXF9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
s_lshr_b32 ttmp8, ttmp8, 12
// SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
// VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
+// GXF9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
v_mov_b32_e32 v1, ttmp8
// SICI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
// VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
+// GXF9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
s_mov_b32 m0, ttmp8
// SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
// VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
+// GXF9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
s_mov_b32 ttmp10, 0
// SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
// VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
+// GXF9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
s_mov_b32 ttmp11, 0x01024fac
// SICI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
// VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
+// GXF9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
s_mov_b32 ttmp8, m0
// SICI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x03,0xf8,0xbe]
// VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
+// GXF9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
s_mov_b32 ttmp8, tma_lo
// SICI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x03,0xf8,0xbe]
// VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
+// NOGFX9: error: not a valid operand
s_mul_i32 ttmp8, 0x00000324, ttmp8
// SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
// VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
+// GXF9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
s_or_b32 ttmp9, ttmp9, 0x00280000
// SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
// VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
+// GXF9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
+
+// ttmp12..ttmp15 (GFX9 only)
+
+s_add_u32 ttmp0, ttmp12, 4
+// NOSICIVI: error: not a valid operand
+// GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
+
+s_add_u32 ttmp0, ttmp13, 4
+// NOSICIVI: error: not a valid operand
+// GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
+
+s_add_u32 ttmp0, ttmp14, 4
+// NOSICIVI: error: not a valid operand
+// GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
+
+s_add_u32 ttmp0, ttmp15, 4
+// NOSICIVI: error: not a valid operand
+// GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
//===----------------------------------------------------------------------===//
// Trap Handler related - Pairs and quadruples of registers
@@ -101,31 +147,47 @@ s_or_b32 ttmp9, ttmp9, 0x00280000
s_mov_b64 ttmp[4:5], exec
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
+// GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
s_mov_b64 [ttmp4,ttmp5], exec
// SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
+// GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
s_mov_b64 exec, [ttmp4,ttmp5]
// SICI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x04,0xfe,0xbe]
// VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
+// GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
s_mov_b64 tba, ttmp[4:5]
// SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe]
// VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
+// NOGFX9: error: not a valid operand
s_mov_b64 ttmp[4:5], tba
// SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
+// NOGFX9: error: not a valid operand
s_mov_b64 tma, ttmp[4:5]
// SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe]
// VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
+// NOGFX9: error: not a valid operand
s_mov_b64 ttmp[4:5], tma
// SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
+// NOGFX9: error: not a valid operand
+
+// ttmp12..ttmp15 (GFX9 only)
+
+s_mov_b64 ttmp[12:13], exec
+// NOSICIVI: error: not a valid operand
+// GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
+s_mov_b64 ttmp[14:15], exec
+// NOSICIVI: error: not a valid operand
+// GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
//===----------------------------------------------------------------------===//
// Trap Handler related - Some specific instructions
@@ -134,11 +196,20 @@ s_mov_b64 ttmp[4:5], tma
s_setpc_b64 [ttmp2,ttmp3]
// SICI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x20,0x80,0xbe]
// VI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x1d,0x80,0xbe]
+// GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
v_readfirstlane_b32 ttmp8, v1
// SICI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
// VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
+// GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
-buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
-// SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
-// VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
+buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
+// SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
+// VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
+// GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
+
+// ttmp12..ttmp15 (GFX9 only)
+
+buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
+// NOSICIVI: error: not a valid operand
+// GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
Modified: llvm/trunk/test/MC/AMDGPU/vop1-gfx9-err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop1-gfx9-err.s?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop1-gfx9-err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop1-gfx9-err.s Mon Dec 11 07:23:20 2017
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
Modified: llvm/trunk/test/MC/AMDGPU/vop_sdwa.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop_sdwa.s?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop_sdwa.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop_sdwa.s Mon Dec 11 07:23:20 2017
@@ -694,6 +694,11 @@ v_mov_b32 v1, exec dst_sel:BYTE_0 dst_un
// NOSICI: error:
// NOVI: error:
+// GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
+v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+
+// NOSICI: error:
+// NOVI: error:
// GFX9: v_add_f32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x85,0x02]
v_add_f32 v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
@@ -709,6 +714,16 @@ v_add_f32 v0, exec, vcc dst_sel:DWORD ds
// NOSICI: error:
// NOVI: error:
+// NO: error: not a valid operand
+v_add_f32 v0, v1, tba_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
+// NO: error: not a valid operand
+v_add_f32 v0, v1, tma_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
// GFX9: v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x85,0x02]
v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
@@ -719,6 +734,26 @@ v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:
// NOSICI: error:
// NOVI: error:
+// GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
+v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
+// NO: error: not a valid operand
+v_cmp_eq_f32_sdwa tba, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
+// NO: error: not a valid operand
+v_cmp_eq_f32_sdwa tma, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
+// GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
+v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2
+
+// NOSICI: error:
+// NOVI: error:
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32_sdwa vcc, exec, vcc src0_sel:WORD_1 src1_sel:BYTE_2
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt?rev=320375&r1=320374&r2=320375&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt Mon Dec 11 07:23:20 2017
@@ -450,6 +450,9 @@
# GFX9: v_mov_b32_sdwa v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x86,0x06]
0xf9 0x02 0x02 0x7e 0x02 0x10 0x86 0x06
+# GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
+0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06
+
# GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x06]
0xf9 0x02 0x02 0x7e 0x7e 0x10 0x86 0x06
@@ -465,6 +468,9 @@
# GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
0xf9 0x2c 0x84 0x7c 0x01 0x00 0x05 0x82
+# GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
+0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82
+
#===------------------------------------------------------------------------===#
# VOPC with arbitrary SGPR destination
#===------------------------------------------------------------------------===#
@@ -472,6 +478,9 @@
# GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02]
0xf9 0x04 0x84 0x7c 0x01 0x82 0x05 0x02
+# GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
+0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02
+
# GFX9: v_cmp_eq_f32_sdwa exec, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xfe,0x05,0x02]
0xf9 0x04 0x84 0x7c 0x01 0xfe 0x05 0x02
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/trap_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/trap_gfx9.txt?rev=320375&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/trap_gfx9.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/trap_gfx9.txt Mon Dec 11 07:23:20 2017
@@ -0,0 +1,109 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+
+#===----------------------------------------------------------------------===#
+# Trap Handler related - 32 bit registers
+#===----------------------------------------------------------------------===#
+
+# GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
+0x6c,0x84,0x6c,0x80
+
+# GFX9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
+0x88,0x70,0x70,0x80
+
+# GFX9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
+0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00
+
+# GFX9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
+0x70,0x84,0x70,0x80
+
+# GFX9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
+0x74,0x70,0x70,0x80
+
+# GFX9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00]
+0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00
+
+# GFX9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
+0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00
+
+# GFX9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x74,0x75,0x86]
+0x75,0x74,0x75,0x86
+
+# GFX9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
+0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01
+
+# GFX9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
+0x74,0x80,0x00,0xbf
+
+# GFX9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
+0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00
+
+# GFX9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
+0x74,0x8c,0x74,0x8f
+
+# GFX9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
+0x74,0x02,0x02,0x7e
+
+# GFX9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
+0x74,0x00,0xfc,0xbe
+
+# GFX9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
+0x80,0x00,0xf6,0xbe
+
+# GFX9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
+0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01
+
+# GFX9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
+0x7c,0x00,0xf4,0xbe
+
+# GFX9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
+0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00
+
+# GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
+0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00
+
+# GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
+0x78,0x84,0x6c,0x80
+
+# GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
+0x79,0x84,0x6c,0x80
+
+# GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
+0x7a,0x84,0x6c,0x80
+
+# GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
+0x7b,0x84,0x6c,0x80
+
+#===----------------------------------------------------------------------===#
+# Trap Handler related - Pairs of registers
+#===----------------------------------------------------------------------===#
+
+# GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
+0x7e,0x01,0xf0,0xbe
+
+# GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
+0x7e,0x01,0xf0,0xbe
+
+# GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
+0x70,0x01,0xfe,0xbe
+
+# GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
+0x7e,0x01,0xf8,0xbe
+
+# GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
+0x7e,0x01,0xfa,0xbe
+
+#===----------------------------------------------------------------------===#
+# Trap Handler related - Some specific instructions and quadruples of registers
+#===----------------------------------------------------------------------===#
+
+# GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
+0x6e,0x1d,0x80,0xbe
+
+# GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
+0x01,0x05,0xe8,0x7e
+
+# GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
+0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8
+
+# GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
+0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8
More information about the llvm-commits
mailing list