[lld] r320372 - [ELF] Improve comments in aarch64 errata fix test [NFC]

[Peter Smith via llvm-commits]

Author: psmith
Date: Mon Dec 11 07:00:58 2017
New Revision: 320372

URL: http://llvm.org/viewvc/llvm-project?rev=320372&view=rev
Log:
[ELF] Improve comments in aarch64 errata fix test [NFC]

Comment improvements split out from review D36749. No changes to any non
comment line.

Modified:
    lld/trunk/test/ELF/aarch64-cortex-a53-843419-address.s

Modified: lld/trunk/test/ELF/aarch64-cortex-a53-843419-address.s
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/aarch64-cortex-a53-843419-address.s?rev=320372&r1=320371&r2=320372&view=diff
==============================================================================
--- lld/trunk/test/ELF/aarch64-cortex-a53-843419-address.s (original)
+++ lld/trunk/test/ELF/aarch64-cortex-a53-843419-address.s Mon Dec 11 07:00:58 2017
@@ -7,31 +7,31 @@
 // RUN: ld.lld --script %t.script -fix-cortex-a53-843419 -verbose %t.o -o %t2 | FileCheck %s
 
 // Test cases for Cortex-A53 Erratum 843419 that involve interactions
-// between the generated patches and the address of sections
+// between the generated patches and the address of sections.
 
 // See ARM-EPM-048406 Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
 // for full erratum details.
 // In Summary
 // 1.)
-// ADRP (0xff8 or 0xffc)
+// ADRP (0xff8 or 0xffc).
 // 2.)
-// - load or store single register or either integer or vector registers
-// - STP or STNP of either vector or vector registers
-// - Advanced SIMD ST1 store instruction
-// Must not write Rn
-// 3.) optional instruction, can't be a branch, must not write Rn, may read Rn
+// - load or store single register or either integer or vector registers.
+// - STP or STNP of either vector or vector registers.
+// - Advanced SIMD ST1 store instruction.
+// - Must not write Rn.
+// 3.) optional instruction, can't be a branch, must not write Rn, may read Rn.
 // 4.) A load or store instruction from the Load/Store register unsigned
-// immediate class using Rn as the base register
+// immediate class using Rn as the base register.
 
 // An aarch64 section can contain ranges of literal data embedded within the
 // code, these ranges are encoded with mapping symbols. This tests that we
-// can match the erratum sequence in code, but not data
+// can match the erratum sequence in code, but not data.
 // - We can handle more than one patch per code range (denoted by mapping
-//   symbols)
+//   symbols).
 // - We can handle a patch in more than range of code, with literal data
-//   inbetween
+//   inbetween.
 // - We can handle redundant mapping symbols (two or more consecutive mapping
-//   symbols with the same type)
+//   symbols with the same type).
 // - We can ignore erratum sequences in multiple literal data ranges.
 
 // CHECK: detected cortex-a53-843419 erratum sequence starting at FF8 in unpatched output.
@@ -47,10 +47,9 @@ t3_ff8_ldr:
         ldr x0, [x0, :got_lo12:dat]
         ret
 
-
         // create a redundant mapping symbol as we are already in a $x range
         // some object producers unconditionally generate a mapping symbol on
-        // every symbol so we need to handle the case of $x $x
+        // every symbol so we need to handle the case of $x $x.
         .local $x.999
 $x.999:
 // CHECK-NEXT: detected cortex-a53-843419 erratum sequence starting at 1FFC in unpatched output.
@@ -63,7 +62,7 @@ t3_ffc_ldrsimd:
         ldr x2, [x0, :got_lo12:dat]
         ret
 
-// Inline data containing bit pattern of erratum sequence, expect no patch
+// Inline data containing bit pattern of erratum sequence, expect no patch.
         .globl t3_ffc_ldralldata
         .type t3_ff8_ldralldata, %function
         .space 4096 - 20
@@ -83,7 +82,7 @@ t3_ff8_ldralldata:
         .byte 0x00
         .byte 0x40
         .byte 0xf9
-        // Check that we can recognise the erratum sequence post literal data
+        // Check that we can recognise the erratum sequence post literal data.
 
 // CHECK-NEXT: detected cortex-a53-843419 erratum sequence starting at 3FF8 in unpatched output.
 
@@ -100,8 +99,8 @@ t3_ff8_ldralldata:
         .space 4096 - 12
 
         // Start a new InputSectionDescription (see Linker Script) so the
-        // start address will be
-        // affected by any patches added to previous InputSectionDescription
+        // start address will be affected by any patches added to previous
+        // InputSectionDescription.
 
 // CHECK: detected cortex-a53-843419 erratum sequence starting at 4FFC in unpatched output.
 
@@ -118,8 +117,8 @@ t3_ffc_str:
 // CHECK:  detected cortex-a53-843419 erratum sequence starting at 5FF8 in unpatched output.
 
         // Start a new OutputSection (see Linker Script) so the
-        // start address will be
-        // affected by any patches added to previous InputSectionDescription
+        // start address will be affected by any patches added to previous
+        // InputSectionDescription.
         .section .newos, "ax", %progbits
         .globl t3_ff8_str
         .type t3_ff8_str, %function