[llvm] r320368 - [PowerPC] Sign-extend negative constant stores

[Nemanja Ivanovic via llvm-commits]

Author: nemanjai
Date: Mon Dec 11 06:35:48 2017
New Revision: 320368

URL: http://llvm.org/viewvc/llvm-project?rev=320368&view=rev
Log:
[PowerPC] Sign-extend negative constant stores

Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
    llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=320368&r1=320367&r2=320368&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Dec 11 06:35:48 2017
@@ -12228,8 +12228,12 @@ SDValue PPCTargetLowering::PerformDAGCom
     EVT VT = N->getOperand(1).getValueType();
     if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() &&
         isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) {
-      SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl,
-                                        MVT::i64);
+      // Need to sign-extended to 64-bits to handle negative values.
+      EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT();
+      uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1),
+                                    MemVT.getSizeInBits());
+      SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);
+
       // DAG.getTruncStore() can't be used here because it doesn't accept
       // the general (base + offset) addressing mode.
       // So we use UpdateNodeOperands and setTruncatingStore instead.

Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll?rev=320368&r1=320367&r2=320368&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll Mon Dec 11 06:35:48 2017
@@ -105,10 +105,8 @@ entry:
   store i32 %conv1, i32* @glob
   ret void
 ; CHECK-LABEL: @test_igeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
 ; CHECK: blr
 }
 

Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll?rev=320368&r1=320367&r2=320368&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll Mon Dec 11 06:35:48 2017
@@ -105,10 +105,8 @@ entry:
   store i32 %sub, i32* @glob
   ret void
 ; CHECK-LABEL: @test_llgeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
 ; CHECK: blr
 }