[llvm] r320350 - [mips] Removal of microMIPS64R6
Aleksandar Beserminji via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 03:21:40 PST 2017
Author: abeserminji
Date: Mon Dec 11 03:21:40 2017
New Revision: 320350
URL: http://llvm.org/viewvc/llvm-project?rev=320350&view=rev
Log:
[mips] Removal of microMIPS64R6
All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.
This is LLVM part of patch.
Differential Revision: https://reviews.llvm.org/D35625
Added:
llvm/trunk/test/CodeGen/Mips/micromips64r6-unsupported.ll
llvm/trunk/test/MC/Mips/micromips64r6-unsupported.s
Removed:
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/
llvm/trunk/test/MC/Mips/micromips64r6/
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/lib/Target/Mips/Relocation.txt
llvm/trunk/test/CodeGen/Mips/countleading.ll
llvm/trunk/test/CodeGen/Mips/fcmp.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll
llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll
llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
llvm/trunk/test/CodeGen/Mips/mips64shift.ll
llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll
llvm/trunk/test/MC/Mips/mips64extins.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Dec 11 03:21:40 2017
@@ -512,6 +512,9 @@ public:
IsLittleEndian = false;
else
IsLittleEndian = true;
+
+ if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
+ report_fatal_error("microMIPS64R6 is not supported", false);
}
/// True if all of $fcc0 - $fcc7 exist for the current ISA.
@@ -1987,9 +1990,7 @@ bool MipsAsmParser::processInstruction(M
case Mips::DDIV:
case Mips::DDIVU:
case Mips::DIVU_MMR6:
- case Mips::DDIVU_MM64R6:
case Mips::DIV_MMR6:
- case Mips::DDIV_MM64R6:
if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
@@ -5114,8 +5115,6 @@ MipsAsmParser::checkEarlyTargetMatchPred
return Match_Success;
case Mips::DATI:
case Mips::DAHI:
- case Mips::DATI_MM64R6:
- case Mips::DAHI_MM64R6:
if (static_cast<MipsOperand &>(*Operands[1])
.isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
return Match_Success;
@@ -5128,7 +5127,6 @@ unsigned MipsAsmParser::checkTargetMatch
// As described by the MIPSR6 spec, daui must not use the zero operand for
// its source operand.
case Mips::DAUI:
- case Mips::DAUI_MM64R6:
if (Inst.getOperand(1).getReg() == Mips::ZERO ||
Inst.getOperand(1).getReg() == Mips::ZERO_64)
return Match_RequiresNoZeroRegister;
@@ -5201,8 +5199,7 @@ unsigned MipsAsmParser::checkTargetMatch
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
return Match_RequiresDifferentOperands;
return Match_Success;
- case Mips::DINS:
- case Mips::DINS_MM64R6: {
+ case Mips::DINS: {
assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
"Operands must be immediates for dins!");
const signed Pos = Inst.getOperand(2).getImm();
@@ -5212,9 +5209,7 @@ unsigned MipsAsmParser::checkTargetMatch
return Match_Success;
}
case Mips::DINSM:
- case Mips::DINSM_MM64R6:
- case Mips::DINSU:
- case Mips::DINSU_MM64R6: {
+ case Mips::DINSU: {
assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
"Operands must be immediates for dinsm/dinsu!");
const signed Pos = Inst.getOperand(2).getImm();
@@ -5223,8 +5218,7 @@ unsigned MipsAsmParser::checkTargetMatch
return Match_RequiresPosSizeRange33_64;
return Match_Success;
}
- case Mips::DEXT:
- case Mips::DEXT_MM64R6: {
+ case Mips::DEXT: {
assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
"Operands must be immediates for DEXTM!");
const signed Pos = Inst.getOperand(2).getImm();
@@ -5234,9 +5228,7 @@ unsigned MipsAsmParser::checkTargetMatch
return Match_Success;
}
case Mips::DEXTM:
- case Mips::DEXTU:
- case Mips::DEXTM_MM64R6:
- case Mips::DEXTU_MM64R6: {
+ case Mips::DEXTU: {
assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
"Operands must be immediates for dextm/dextu!");
const signed Pos = Inst.getOperand(2).getImm();
@@ -6794,6 +6786,9 @@ bool MipsAsmParser::parseSetArchDirectiv
if (ArchFeatureName.empty())
return reportParseError("unsupported architecture");
+ if (ArchFeatureName == "mips64r6" && inMicroMipsMode())
+ return reportParseError("mips64r6 does not support microMIPS");
+
selectArch(ArchFeatureName);
getTargetStreamer().emitDirectiveSetArch(Arch);
return false;
@@ -7125,6 +7120,10 @@ bool MipsAsmParser::parseDirectiveSet()
Parser.eatToEndOfStatement();
return false;
} else if (Tok.getString() == "micromips") {
+ if (hasMips64r6()) {
+ Error(Tok.getLoc(), ".set micromips directive is not supported with MIPS64R6");
+ return false;
+ }
return parseSetFeature(Mips::FeatureMicroMips);
} else if (Tok.getString() == "mips0") {
return parseSetMips0Directive();
@@ -7157,6 +7156,10 @@ bool MipsAsmParser::parseDirectiveSet()
} else if (Tok.getString() == "mips64r5") {
return parseSetFeature(Mips::FeatureMips64r5);
} else if (Tok.getString() == "mips64r6") {
+ if (inMicroMipsMode()) {
+ Error(Tok.getLoc(), "MIPS64R6 is not supported with microMIPS");
+ return false;
+ }
return parseSetFeature(Mips::FeatureMips64r6);
} else if (Tok.getString() == "dsp") {
return parseSetFeature(Mips::FeatureDSP);
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon Dec 11 03:21:40 2017
@@ -1068,26 +1068,16 @@ static DecodeStatus DecodeDEXT(MCInst &M
unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
unsigned Size = 0;
unsigned Pos = 0;
- bool IsMicroMips = false;
switch (MI.getOpcode()) {
- case Mips::DEXT_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DEXT:
Pos = Lsb;
Size = Msbd + 1;
break;
- case Mips::DEXTM_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DEXTM:
Pos = Lsb;
Size = Msbd + 1 + 32;
break;
- case Mips::DEXTU_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DEXTU:
Pos = Lsb + 32;
Size = Msbd + 1;
@@ -1096,14 +1086,10 @@ static DecodeStatus DecodeDEXT(MCInst &M
llvm_unreachable("Unknown DEXT instruction!");
}
- MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT);
+ MI.setOpcode(Mips::DEXT);
- // Although the format of the instruction is similar, rs and rt are swapped
- // for microMIPS64R6.
InsnType Rs = fieldFromInstruction(Insn, 21, 5);
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
- if (IsMicroMips)
- std::swap(Rs, Rt);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
@@ -1122,26 +1108,16 @@ static DecodeStatus DecodeDINS(MCInst &M
unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
unsigned Size = 0;
unsigned Pos = 0;
- bool IsMicroMips = false;
switch (MI.getOpcode()) {
- case Mips::DINS_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DINS:
Pos = Lsb;
Size = Msbd + 1 - Pos;
break;
- case Mips::DINSM_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DINSM:
Pos = Lsb;
Size = Msbd + 33 - Pos;
break;
- case Mips::DINSU_MM64R6:
- IsMicroMips = true;
- LLVM_FALLTHROUGH;
case Mips::DINSU:
Pos = Lsb + 32;
// mbsd = pos + size - 33
@@ -1152,14 +1128,10 @@ static DecodeStatus DecodeDINS(MCInst &M
llvm_unreachable("Unknown DINS instruction!");
}
- // Although the format of the instruction is similar, rs and rt are swapped
- // for microMIPS64R6.
InsnType Rs = fieldFromInstruction(Insn, 21, 5);
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
- if (IsMicroMips)
- std::swap(Rs, Rt);
- MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS);
+ MI.setOpcode(Mips::DINS);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(MCOperand::createImm(Pos));
@@ -1240,7 +1212,7 @@ DecodeStatus MipsDisassembler::getInstru
if (hasMips32r6()) {
DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
// Calling the auto-generated decoder function for microMIPS32R6
- // (and microMIPS64R6) 16-bit instructions.
+ // 16-bit instructions.
Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
Address, this, STI);
if (Result != MCDisassembler::Fail) {
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Mon Dec 11 03:21:40 2017
@@ -86,18 +86,6 @@ static void LowerLargeShift(MCInst& Inst
case Mips::DROTR:
Inst.setOpcode(Mips::DROTR32);
return;
- case Mips::DSLL_MM64R6:
- Inst.setOpcode(Mips::DSLL32_MM64R6);
- return;
- case Mips::DSRL_MM64R6:
- Inst.setOpcode(Mips::DSRL32_MM64R6);
- return;
- case Mips::DSRA_MM64R6:
- Inst.setOpcode(Mips::DSRA32_MM64R6);
- return;
- case Mips::DROTR_MM64R6:
- Inst.setOpcode(Mips::DROTR32_MM64R6);
- return;
}
}
@@ -178,10 +166,6 @@ encodeInstruction(const MCInst &MI, raw_
case Mips::DSRL:
case Mips::DSRA:
case Mips::DROTR:
- case Mips::DSLL_MM64R6:
- case Mips::DSRL_MM64R6:
- case Mips::DSRA_MM64R6:
- case Mips::DROTR_MM64R6:
LowerLargeShift(TmpInst);
break;
// Compact branches, enforce encoding restrictions.
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Mon Dec 11 03:21:40 2017
@@ -17,7 +17,7 @@ class MMR6Arch<string opstr> {
string DecoderNamespace = "MicroMipsR6";
}
-// Class used for microMIPS32r6 and microMIPS64r6 instructions.
+// Class used for microMIPS32r6 instructions.
class MicroMipsR6Inst16 : PredicateControl {
string DecoderNamespace = "MicroMipsR6";
let InsnPredicates = [HasMicroMips32r6];
Removed: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td?rev=320349&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td (removed)
@@ -1,267 +0,0 @@
-//=- MicroMips64r6InstrFormats.td - Instruction Formats -*- tablegen -* -=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes microMIPS64r6 instruction formats.
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_FM_MMR6 {
- bits<5> rt;
- bits<5> rs;
- bits<16> imm;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b111100;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-0} = imm;
-}
-
-class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> {
- bits<5> rs;
- bits<16> imm;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010000;
- let Inst{25-21} = funct;
- let Inst{20-16} = rs;
- let Inst{15-0} = imm;
-}
-
-class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> {
- bits<5> rt;
- bits<5> rs;
- bits<5> size;
- bits<5> pos;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = size;
- let Inst{10-6} = pos;
- let Inst{5-0} = funct;
-}
-
-class POOL32S_DALIGN_FM_MMR6 {
- bits<5> rs;
- bits<5> rt;
- bits<5> rd;
- bits<3> bp;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rs;
- let Inst{20-16} = rt;
- let Inst{15-11} = rd;
- let Inst{10-8} = bp;
- let Inst{7-6} = 0b00;
- let Inst{5-0} = 0b011100;
-}
-
-class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
- : MMR6Arch<instr_asm> {
- bits<5> rt;
- bits<5> rs;
- bits<5> rd;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = rd;
- let Inst{10-9} = 0b00;
- let Inst{8-0} = funct;
-}
-
-class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<5> rs;
- bits<3> sel;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-14} = 0;
- let Inst{13-11} = sel;
- let Inst{10-6} = funct;
- let Inst{5-0} = 0b111100;
-}
-
-class POOL32S_ARITH_FM_MMR6<string opstr, bits<9> funct>
- : MMR6Arch<opstr> {
- bits<5> rt;
- bits<5> rs;
- bits<5> rd;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = rd;
- let Inst{10-9} = 0b00;
- let Inst{8-0} = funct;
-}
-
-class DADDIU_FM_MMR6<string opstr> : MMR6Arch<opstr> {
- bits<5> rt;
- bits<5> rs;
- bits<16> imm16;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010111;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-0} = imm16;
-}
-
-class PCREL18_FM_MMR6<bits<3> funct> : MipsR6Inst {
- bits<5> rt;
- bits<18> imm;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b011110;
- let Inst{25-21} = rt;
- let Inst{20-18} = funct;
- let Inst{17-0} = imm;
-}
-
-class POOL32S_2R_FM_MMR6<string instr_asm, bits<10> funct>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<5> rs;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-6} = funct;
- let Inst{5-0} = 0b111100;
-}
-
-class POOL32S_2RSA5B0_FM_MMR6<string instr_asm, bits<9> funct>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<5> rs;
- bits<5> sa;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = sa;
- let Inst{10-9} = 0b00;
- let Inst{8-0} = funct;
-}
-
-class LD_SD_32_2R_OFFSET16_FM_MMR6<string instr_asm, bits<6> op>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<21> addr;
- bits<5> base = addr{20-16};
- bits<16> offset = addr{15-0};
-
- bits<32> Inst;
-
- let Inst{31-26} = op;
- let Inst{25-21} = rt;
- let Inst{20-16} = base;
- let Inst{15-0} = offset;
-}
-
-class POOL32C_2R_OFFSET12_FM_MMR6<string instr_asm, bits<4> funct>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<21> addr;
- bits<5> base = addr{20-16};
- bits<12> offset = addr{11-0};
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b011000;
- let Inst{25-21} = rt;
- let Inst{20-16} = base;
- let Inst{15-12} = funct;
- let Inst{11-0} = offset;
-}
-
-class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- bits<5> rt;
- bits<5> rs;
- bits<5> rd;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = rd;
- let Inst{10-9} = 0b00;
- let Inst{8-0} = funct;
-}
-
-class POOL32S_DBITSWAP_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
- MipsR6Inst {
- bits<5> rt;
- bits<5> rd;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rd;
- let Inst{15-12} = 0b0000;
- let Inst{11-6} = 0b101100;
- let Inst{5-0} = 0b111100;
-}
-
-class POOL32S_3RSA_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
- MipsR6Inst {
- bits<5> rt;
- bits<5> rs;
- bits<5> rd;
- bits<2> sa;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b010110;
- let Inst{25-21} = rt;
- let Inst{20-16} = rs;
- let Inst{15-11} = rd;
- let Inst{10-9} = sa;
- let Inst{8-6} = 0b100;
- let Inst{5-0} = 0b000100;
-}
-
-class PCREL_1ROFFSET19_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
- MipsR6Inst {
- bits<5> rt;
- bits<19> offset;
-
- bits<32> Inst;
-
- let Inst{31-26} = 0b011110;
- let Inst{25-21} = rt;
- let Inst{20-19} = 0b10;
- let Inst{18-0} = offset;
-}
Removed: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=320349&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (removed)
@@ -1,581 +0,0 @@
-//=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes MicroMips64r6 instructions.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Encodings
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_MMR6_ENC : DAUI_FM_MMR6;
-class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
-class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
-class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
-class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
-class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
-class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
-class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
-class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
-class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
-class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
-class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
-class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
-class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
-class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
-class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
-class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
-class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
-class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
-class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
-class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
-class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
-class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
-class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
-class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
-class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
-class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
-class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
-class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
-class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
-class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dsbh", 0b0111101100>;
-class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
-class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll", 0b000000000>;
-class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll32", 0b000001000>;
-class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsllv", 0b000010000>;
-class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
-class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra", 0b010000000>;
-class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra32", 0b010000100>;
-class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
-class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
-class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
-class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
-class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
-class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
-class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
-class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
-class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
-class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
-class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
-class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
-class DBITSWAP_MM64R6_ENC : POOL32S_DBITSWAP_FM_MMR6<"dbitswap">;
-class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6<"dlsa">;
-class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6<"lwupc">;
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Descriptions
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- dag OutOperandList = (outs GPROpnd:$rt);
- dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
- string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
- list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
-}
-class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
-
-class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- dag OutOperandList = (outs GPROpnd:$rs);
- dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm);
- string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
- string Constraints = "$rs = $rt";
- InstrItinClass Itinerary = Itin;
-}
-class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
-class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
-
-class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
- Operand SizeOpnd, SDPatternOperator Op = null_frag>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- dag OutOperandList = (outs RO:$rt);
- dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
- string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
- list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
- InstrItinClass Itinerary = II_EXT;
- Format Form = FrmR;
- string BaseOpcode = instr_asm;
-}
-class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
- uimm5_plus1_report_uimm6, MipsExt>;
-class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
- uimm5_plus33, MipsExt>;
-class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
- uimm5_plus1, MipsExt>;
-
-class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass itin>
- : MMR6Arch<instr_asm>, MipsR6Inst {
- dag OutOperandList = (outs GPROpnd:$rd);
- dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
- string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
- list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
-}
-
-class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3,
- II_DALIGN>;
-
-class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV,
- sdiv>;
-class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, II_DMOD,
- srem>;
-class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU,
- udiv>;
-class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU,
- urem>;
-
-class DCLO_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins GPR64Opnd:$rs);
- string AsmString = !strconcat("dclo", "\t$rt, $rs");
- list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
- InstrItinClass Itinerary = II_DCLO;
- Format Form = FrmR;
- string BaseOpcode = "dclo";
-}
-
-class DCLZ_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins GPR64Opnd:$rs);
- string AsmString = !strconcat("dclz", "\t$rt, $rs");
- list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
- InstrItinClass Itinerary = II_DCLZ;
- Format Form = FrmR;
- string BaseOpcode = "dclz";
-}
-
-class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
- uimm5_inssize_plus1, immZExt5Plus32,
- immZExt5Plus1>;
-class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
- immZExt5, immZExtRange2To64>;
-class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5_report_uimm6,
- uimm5_inssize_plus1, immZExt5, immZExt5Plus1>;
-class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
- II_DMTC0>;
-class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
- II_DMTC1, bitconvert>;
-class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd,
- II_DMTC2>;
-class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd,
- II_DMFC0>;
-class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
- II_DMFC1, bitconvert>;
-class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd,
- II_DMFC2>;
-class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
-class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
- II_DADDIU, immSExt16, add>,
- IsAsCheapAsAMove;
-class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
-
-class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
- InstrItinClass Itin = NoItinerary,
- SDPatternOperator OpNode = null_frag>
- : MipsR6Inst {
- dag OutOperandList = (outs RO:$rd);
- dag InOperandList = (ins RO:$rs, RO:$rt);
- string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
- list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
- InstrItinClass Itinerary = Itin;
- Format Form = FrmR;
- string BaseOpcode = instr_asm;
- let isCommutable = 0;
- let isReMaterializable = 1;
- let TwoOperandAliasConstraint = "$rd = $rs";
-}
-class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
-class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
-
-class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3,
- II_LDPC>;
-
-class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
- InstrItinClass Itin = NoItinerary,
- SDPatternOperator Op = null_frag> : MipsR6Inst {
- dag OutOperandList = (outs GPROpnd:$rd);
- dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
- string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
- InstrItinClass Itinerary = Itin;
- list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
-}
-
-class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
-class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
- mulhs>;
-class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
-class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
- mulhu>;
-
-class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin> {
- dag OutOperandList = (outs GPROpnd:$rt);
- dag InOperandList = (ins GPROpnd:$rs);
- string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
- bit hasSideEffects = 0;
- list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
- Format Form = FrmR;
- string BaseOpcode = instr_asm;
-}
-
-class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd, II_DSBH>;
-class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd, II_DSHD>;
-
-class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
- InstrItinClass itin,
- SDPatternOperator OpNode = null_frag,
- SDPatternOperator PO = null_frag> {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
- string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
- list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
- InstrItinClass Itinerary = itin;
- Format Form = FrmR;
- string TwoOperandAliasConstraint = "$rs = $rt";
- string BaseOpcode = instr_asm;
-}
-
-class SHIFT_ROTATE_REG_MM64R6<string instr_asm, InstrItinClass itin,
- SDPatternOperator OpNode = null_frag> {
- dag OutOperandList = (outs GPR64Opnd:$rd);
- dag InOperandList = (ins GPR64Opnd:$rt, GPR32Opnd:$rs);
- string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
- list<dag> Pattern = [(set GPR64Opnd:$rd,
- (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
- InstrItinClass Itinerary = itin;
- Format Form = FrmR;
- string BaseOpcode = instr_asm;
-}
-
-class DSLL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll", uimm6, II_DSLL, shl,
- immZExt6>;
-class DSLL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll32", uimm5, II_DSLL32>;
-class DSLLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsllv", II_DSLLV, shl>;
-class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
-class DSRA_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra", uimm6, II_DSRA, sra,
- immZExt6>;
-class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
-class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
- rotr, immZExt6>;
-class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
- II_DROTR32>;
-class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
-class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
- immZExt6>;
-class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
-class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
-
-class Load_MM64R6<string instr_asm, Operand MemOpnd, InstrItinClass itin,
- SDPatternOperator OpNode = null_frag> {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins MemOpnd:$addr);
- string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
- list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
- InstrItinClass Itinerary = itin;
- Format Form = FrmI;
- bit mayLoad = 1;
- bit canFoldAsLoad = 1;
- string BaseOpcode = instr_asm;
-}
-
-class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
- string DecoderMethod = "DecodeMemMMImm16";
-}
-class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
- string DecoderMethod = "DecodeMemMMImm12";
-}
-
-class LLD_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins mem_simm12:$addr);
- string AsmString = "lld\t$rt, $addr";
- list<dag> Pattern = [];
- bit mayLoad = 1;
- InstrItinClass Itinerary = II_LLD;
- string BaseOpcode = "lld";
- string DecoderMethod = "DecodeMemMMImm12";
-}
-
-class SD_MM64R6_DESC {
- dag OutOperandList = (outs);
- dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
- string AsmString = "sd\t$rt, $addr";
- list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
- InstrItinClass Itinerary = II_SD;
- Format Form = FrmI;
- bit mayStore = 1;
- string BaseOpcode = "sd";
- string DecoderMethod = "DecodeMemMMImm16";
-}
-
-class DBITSWAP_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rd);
- dag InOperandList = (ins GPR64Opnd:$rt);
- string AsmString = !strconcat("dbitswap", "\t$rd, $rt");
- list<dag> Pattern = [];
- InstrItinClass Itinerary = II_DBITSWAP;
-}
-
-class DLSA_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rd);
- dag InOperandList = (ins GPR64Opnd:$rt, GPR64Opnd:$rs, uimm2_plus1:$sa);
- string AsmString = "dlsa\t$rt, $rs, $rd, $sa";
- list<dag> Pattern = [];
- InstrItinClass Itinerary = II_DLSA;
-}
-
-class LWUPC_MM64R6_DESC {
- dag OutOperandList = (outs GPR64Opnd:$rt);
- dag InOperandList = (ins simm19_lsl2:$offset);
- string AsmString = "lwupc\t$rt, $offset";
- list<dag> Pattern = [];
- InstrItinClass Itinerary = II_LWUPC;
- bit mayLoad = 1;
- bit IsPCRelativeLoad = 1;
-}
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Definitions
-//
-//===----------------------------------------------------------------------===//
-
-let DecoderNamespace = "MicroMipsR6" in {
- def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
- let DecoderMethod = "DecodeDAHIDATIMMR6" in {
- def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
- def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
- }
- let DecoderMethod = "DecodeDEXT" in {
- def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
- ISA_MICROMIPS64R6;
- def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
- ISA_MICROMIPS64R6;
- def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
- ISA_MICROMIPS64R6;
- }
- def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
- ISA_MICROMIPS64R6;
- def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- let DecoderMethod = "DecodeDINS" in {
- def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- }
- def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
- ISA_MICROMIPS64R6;
- def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_ENC, DSBH_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_ENC, DSHD_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSLL_MM64R6 : StdMMR6Rel, DSLL_MM64R6_ENC, DSLL_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSLL32_MM64R6 : StdMMR6Rel, DSLL32_MM64R6_ENC, DSLL32_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSLLV_MM64R6 : StdMMR6Rel, DSLLV_MM64R6_ENC, DSLLV_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRAV_MM64R6 : StdMMR6Rel, DSRAV_MM64R6_ENC, DSRAV_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRA_MM64R6 : StdMMR6Rel, DSRA_MM64R6_ENC, DSRA_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRA32_MM64R6 : StdMMR6Rel, DSRA32_MM64R6_ENC, DSRA32_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DCLO_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLO_MM64R6_ENC, DCLO_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DCLZ_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLZ_MM64R6_ENC, DCLZ_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_ENC, DROTR_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_ENC, DROTR32_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_ENC, DBITSWAP_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_ENC, DLSA_MM64R6_DESC,
- ISA_MICROMIPS64R6;
- def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_ENC, LWUPC_MM64R6_DESC,
- ISA_MICROMIPS64R6;
-}
-
-let AdditionalPredicates = [InMicroMips] in
-defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
-
-//===----------------------------------------------------------------------===//
-//
-// Arbitrary patterns that map to one or more instructions
-//
-//===----------------------------------------------------------------------===//
-
-defm : MipsHiLoRelocs<LUi64, DADDIU_MM64R6, ZERO_64, GPR64Opnd>, SYM_32,
- ISA_MICROMIPS64R6;
-
-defm : MipsHighestHigherHiLoRelocs<LUi64, DADDIU_MM64R6>, SYM_64,
- ISA_MICROMIPS64R6;
-
-def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
- (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
-def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
- (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
-
-
-def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
- (DROTRV_MM64R6 GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
- ISA_MICROMIPS64R6;
-
-
-def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-
-// Carry pattern
-def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
- (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
-
-def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction aliases
-//
-//===----------------------------------------------------------------------===//
-
-def : MipsInstAlias<"dmtc0 $rt, $rd",
- (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
-def : MipsInstAlias<"dmfc0 $rt, $rd",
- (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"daddu $rs, $rt, $imm",
- (DADDIU_MM64R6 GPR64Opnd:$rs,
- GPR64Opnd:$rt,
- simm16_64:$imm),
- 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"daddu $rs, $imm",
- (DADDIU_MM64R6 GPR64Opnd:$rs,
- GPR64Opnd:$rs,
- simm16_64:$imm),
- 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsubu $rt, $rs, $imm",
- (DADDIU_MM64R6 GPR64Opnd:$rt,
- GPR64Opnd:$rs,
- InvertedImOperand64:$imm),
- 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsubu $rs, $imm",
- (DADDIU_MM64R6 GPR64Opnd:$rs,
- GPR64Opnd:$rs,
- InvertedImOperand64:$imm),
- 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dneg $rt, $rs",
- (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dneg $rt",
- (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dnegu $rt, $rs",
- (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dnegu $rt",
- (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsll $rd, $rt, $rs",
- (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
- GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsrl $rd, $rt, $rs",
- (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
- GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsrl $rd, $rt",
- (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
- GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsll $rd, $rt",
- (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
- GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
- (DINSM_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
- uimm_range_2_64:$size), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
- (DINSU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs,
- uimm5_plus32:$pos, uimm5_plus1:$size), 0>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
- (DEXTM_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
- uimm5_plus33:$size), 0>,
- ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
- (DEXTU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs,
- uimm5_plus32:$pos, uimm5_plus1:$size), 0>,
- ISA_MICROMIPS64R6;
-
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Mon Dec 11 03:21:40 2017
@@ -587,24 +587,24 @@ class UncondBranchMM16<string opstr> :
}
def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
- ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+ ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
- LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
+ LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
- SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+ SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
- SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+ SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
- ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+ ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
- LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
+ LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
@@ -632,7 +632,7 @@ def MFHI16_MM : MoveFromHILOMM<"mfhi", G
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
@@ -647,9 +647,9 @@ def BNEZ16_MM : CBranchZeroMM<"bnez16",
BEQNEZ_FM_MM16<0x2b>;
def B16_MM : UncondBranchMM16<"b16">, B16_FM;
def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
- ISA_MICROMIPS_NOT_32R6_64R6;
+ ISA_MICROMIPS_NOT_32R6;
let DecoderNamespace = "MicroMips" in {
/// Load and Store Instructions - multiple
Modified: llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp Mon Dec 11 03:21:40 2017
@@ -495,8 +495,7 @@ bool MicroMipsSizeReduce::runOnMachineFu
Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
- // TODO: Add support for other subtargets:
- // microMIPS32r6 and microMIPS64r6
+ // TODO: Add support for the subtarget microMIPS32R6.
if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
Subtarget->hasMips32r6())
return false;
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Dec 11 03:21:40 2017
@@ -99,8 +99,8 @@ let DecoderNamespace = "Mips64" in {
def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>,
ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
- def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
- II_DADDIU, immSExt16, add>,
+ def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
+ immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
}
@@ -120,13 +120,13 @@ def LUi64 : LoadUpper<"lui", GPR64Opnd
/// Arithmetic Instructions (3-Operand, R-Type)
let AdditionalPredicates = [NotInMicroMips] in {
- def DADD : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>,
- ADD_FM<0, 0x2c>, ISA_MIPS3;
- def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
- ADD_FM<0, 0x2d>, ISA_MIPS3;
- def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
+ def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
ISA_MIPS3;
- def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
+ def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
+ ADD_FM<0, 0x2d>, ISA_MIPS3;
+ def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
+ ADD_FM<0, 0x2f>, ISA_MIPS3;
+ def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
ISA_MIPS3;
}
@@ -141,40 +141,35 @@ def NOR64 : LogicNOR<"nor", GPR64Opnd>,
/// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in {
- def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
- shl, immZExt6>,
+ def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl,
+ immZExt6>,
SRA_FM<0x38, 0>, ISA_MIPS3;
- def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
- srl, immZExt6>,
+ def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl,
+ immZExt6>,
SRA_FM<0x3a, 0>, ISA_MIPS3;
- def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
- sra, immZExt6>,
+ def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra,
+ immZExt6>,
SRA_FM<0x3b, 0>, ISA_MIPS3;
- def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
+ def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
SRLV_FM<0x14, 0>, ISA_MIPS3;
- def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
+ def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
SRLV_FM<0x17, 0>, ISA_MIPS3;
- def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
+ def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
SRLV_FM<0x16, 0>, ISA_MIPS3;
- def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
- II_DSLL32>,
+ def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
SRA_FM<0x3c, 0>, ISA_MIPS3;
- def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
- II_DSRL32>,
+ def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
SRA_FM<0x3e, 0>, ISA_MIPS3;
- def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
- II_DSRA32>,
+ def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
SRA_FM<0x3f, 0>, ISA_MIPS3;
// Rotate Instructions
- def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR,
- rotr, immZExt6>,
+ def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
+ immZExt6>,
SRA_FM<0x3a, 1>, ISA_MIPS64R2;
- def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV,
- rotr>,
+ def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
SRLV_FM<0x16, 1>, ISA_MIPS64R2;
- def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd,
- II_DROTR32>,
+ def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
SRA_FM<0x3e, 1>, ISA_MIPS64R2;
}
@@ -192,11 +187,11 @@ def SW64 : Store<"sw", GPR64Opnd, trunc
}
let AdditionalPredicates = [NotInMicroMips] in {
- def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
+ def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
LW_FM<0x27>, ISA_MIPS3;
- def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
+ def LD : LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
LW_FM<0x37>, ISA_MIPS3;
- def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
+ def SD : StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
LW_FM<0x3f>, ISA_MIPS3;
}
@@ -221,7 +216,7 @@ def SDR : StoreLeftRight<"sdr", MipsSD
/// Load-linked, Store-conditional
let AdditionalPredicates = [NotInMicroMips] in {
- def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
+ def LLD : LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
ISA_MIPS3_NOT_32R6_64R6;
}
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
@@ -299,10 +294,10 @@ def SEH64 : SignExtInReg<"seh", i16, GPR
/// Count Leading
let AdditionalPredicates = [NotInMicroMips] in {
- def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>,
- CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
- def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>,
- CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
+ def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
+ ISA_MIPS64_NOT_64R6;
+ def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>,
+ ISA_MIPS64_NOT_64R6;
/// Double Word Swap Bytes/HalfWords
def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>,
@@ -568,74 +563,70 @@ defm : MipsHiLoRelocs<LUi64, DADDiu, ZER
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>;
-multiclass MipsHighestHigherHiLoRelocs<Instruction Lui, Instruction Daddiu> {
+// highest/higher/hi/lo relocs
+let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)),
- (JAL texternalsym:$dst)>;
+ (JAL texternalsym:$dst)>, SYM_64;
def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
- (Lui tglobaladdr:$in)>;
+ (LUi64 tglobaladdr:$in)>, SYM_64;
def : MipsPat<(MipsHighest (i64 tblockaddress:$in)),
- (Lui tblockaddress:$in)>;
+ (LUi64 tblockaddress:$in)>, SYM_64;
def : MipsPat<(MipsHighest (i64 tjumptable:$in)),
- (Lui tjumptable:$in)>;
+ (LUi64 tjumptable:$in)>, SYM_64;
def : MipsPat<(MipsHighest (i64 tconstpool:$in)),
- (Lui tconstpool:$in)>;
+ (LUi64 tconstpool:$in)>, SYM_64;
def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)),
- (Lui tglobaltlsaddr:$in)>;
+ (LUi64 tglobaltlsaddr:$in)>, SYM_64;
def : MipsPat<(MipsHighest (i64 texternalsym:$in)),
- (Lui texternalsym:$in)>;
+ (LUi64 texternalsym:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
- (Daddiu ZERO_64, tglobaladdr:$in)>;
+ (DADDiu ZERO_64, tglobaladdr:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 tblockaddress:$in)),
- (Daddiu ZERO_64, tblockaddress:$in)>;
+ (DADDiu ZERO_64, tblockaddress:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 tjumptable:$in)),
- (Daddiu ZERO_64, tjumptable:$in)>;
+ (DADDiu ZERO_64, tjumptable:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 tconstpool:$in)),
- (Daddiu ZERO_64, tconstpool:$in)>;
+ (DADDiu ZERO_64, tconstpool:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)),
- (Daddiu ZERO_64, tglobaltlsaddr:$in)>;
+ (DADDiu ZERO_64, tglobaltlsaddr:$in)>, SYM_64;
def : MipsPat<(MipsHigher (i64 texternalsym:$in)),
- (Daddiu ZERO_64, texternalsym:$in)>;
+ (DADDiu ZERO_64, texternalsym:$in)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+ (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))),
- (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+ (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))),
- (Daddiu GPR64:$hi, tjumptable:$lo)>;
+ (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
- (Daddiu GPR64:$hi, tconstpool:$lo)>;
+ (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))),
- (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+ (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+ (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))),
- (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+ (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))),
- (Daddiu GPR64:$hi, tjumptable:$lo)>;
+ (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))),
- (Daddiu GPR64:$hi, tconstpool:$lo)>;
+ (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))),
- (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+ (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+ (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))),
- (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+ (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))),
- (Daddiu GPR64:$hi, tjumptable:$lo)>;
+ (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))),
- (Daddiu GPR64:$hi, tconstpool:$lo)>;
+ (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64;
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
- (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
-
+ (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64;
}
-// highest/higher/hi/lo relocs
-let AdditionalPredicates = [NotInMicroMips] in
-defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
-
// gp_rel relocs
def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
(DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64;
Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Mon Dec 11 03:21:40 2017
@@ -117,21 +117,21 @@ let AdditionalPredicates = [NotInMicroMi
}
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
- def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
- def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
- def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
+ def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
+ def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
+ def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
- def DLSA_R6 : R6MMR6Rel, DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
+ def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
- def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
+ def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
}
-def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
+def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
let DecoderNamespace = "Mips32r6_64r6_GP64" in {
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Dec 11 03:21:40 2017
@@ -1395,11 +1395,6 @@ MipsTargetLowering::EmitInstrWithCustomI
case Mips::DMOD:
case Mips::DMODU:
return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
- case Mips::DDIV_MM64R6:
- case Mips::DDIVU_MM64R6:
- case Mips::DMOD_MM64R6:
- case Mips::DMODU_MM64R6:
- return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
case Mips::PseudoSELECT_I:
case Mips::PseudoSELECT_I64:
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 11 03:21:40 2017
@@ -593,28 +593,22 @@ bool MipsInstrInfo::verifyInstruction(co
case Mips::INS:
case Mips::INS_MM:
case Mips::DINS:
- case Mips::DINS_MM64R6:
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
case Mips::DINSM:
- case Mips::DINSM_MM64R6:
// The ISA spec has a subtle difference here in that it says:
// 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
// is in line with the rest of instructions.
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
case Mips::DINSU:
- case Mips::DINSU_MM64R6:
// The ISA spec has a subtle difference here in that it says:
// 2 <= size <= 64 for 'dinsm', so we change the bounds so that it
// is in line with the rest of instructions.
return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64);
case Mips::DEXT:
- case Mips::DEXT_MM64R6:
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
case Mips::DEXTM:
- case Mips::DEXTM_MM64R6:
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
case Mips::DEXTU:
- case Mips::DEXTU_MM64R6:
return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
default:
return true;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 11 03:21:40 2017
@@ -208,8 +208,6 @@ def NotMips64r6 : Predicate<"!Subtar
AssemblerPredicate<"!FeatureMips64r6">;
def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
-def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
- AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">;
def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
@@ -313,9 +311,6 @@ class ISA_MICROMIPS { list<Predicate> In
class ISA_MICROMIPS32R6 {
list<Predicate> InsnPredicates = [HasMicroMips32r6];
}
-class ISA_MICROMIPS64R6 {
- list<Predicate> InsnPredicates = [HasMicroMips64r6];
-}
class ISA_MICROMIPS32_NOT_MIPS32R6 {
list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
}
@@ -393,8 +388,8 @@ class ASE_MT {
// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
// It can be used only on instructions that doesn't inherit PredicateControl.
-class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
- let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
+class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
+ let InsnPredicates = [InMicroMips, NotMips32r6];
}
class ASE_NOT_DSP {
@@ -3014,10 +3009,6 @@ include "MicroMipsInstrFPU.td"
include "MicroMips32r6InstrFormats.td"
include "MicroMips32r6InstrInfo.td"
-// Micromips64 r6
-include "MicroMips64r6InstrFormats.td"
-include "MicroMips64r6InstrInfo.td"
-
// Micromips DSP
include "MicroMipsDSPInstrFormats.td"
include "MicroMipsDSPInstrInfo.td"
Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp Mon Dec 11 03:21:40 2017
@@ -41,9 +41,7 @@ unsigned MipsFunctionInfo::getGlobalBase
STI.inMips16Mode()
? &Mips::CPU16RegsRegClass
: STI.inMicroMipsMode()
- ? STI.hasMips64()
- ? &Mips::GPRMM16_64RegClass
- : &Mips::GPRMM16RegClass
+ ? &Mips::GPRMM16RegClass
: static_cast<const MipsTargetMachine &>(MF.getTarget())
.getABI()
.IsN64()
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Dec 11 03:21:40 2017
@@ -54,8 +54,7 @@ MipsRegisterInfo::getPointerRegClass(con
case MipsPtrClass::Default:
return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
case MipsPtrClass::GPR16MM:
- return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass
- : &Mips::GPRMM16RegClass;
+ return &Mips::GPRMM16RegClass;
case MipsPtrClass::StackPointer:
return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
case MipsPtrClass::GlobalPointer:
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Mon Dec 11 03:21:40 2017
@@ -349,12 +349,6 @@ def GPR64 : RegisterClass<"Mips", [i64],
// Reserved
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
-def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
- // Callee save
- S0_64, S1_64,
- // Return Values and Arguments
- V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
-
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
Modified: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td Mon Dec 11 03:21:40 2017
@@ -18,8 +18,8 @@ def MipsP5600Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
HasMips64, HasMips64r2, HasCnMips,
InMicroMips, InMips16Mode,
- HasMicroMips32r6, HasMicroMips64r6,
- HasDSP, HasDSPR2, HasMT];
+ HasMicroMips32r6, HasDSP,
+ HasDSPR2, HasMT];
}
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Mon Dec 11 03:21:40 2017
@@ -104,6 +104,9 @@ MipsSubtarget::MipsSubtarget(const Tripl
if (IsFPXX && (isABI_N32() || isABI_N64()))
report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
+ if (hasMips64r6() && InMicroMipsMode)
+ report_fatal_error("microMIPS64R6 is not supported", false);
+
if (hasMips32r6()) {
StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Mon Dec 11 03:21:40 2017
@@ -265,7 +265,6 @@ public:
}
bool inMicroMipsMode() const { return InMicroMipsMode; }
bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
- bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; }
bool hasDSPR3() const { return HasDSPR3; }
Modified: llvm/trunk/lib/Target/Mips/Relocation.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Relocation.txt?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Relocation.txt (original)
+++ llvm/trunk/lib/Target/Mips/Relocation.txt Mon Dec 11 03:21:40 2017
@@ -69,40 +69,7 @@ to MIPS32 to compute addresses for the s
The instantiation in Mips64InstrInfo.td is used for MIPS64 in ILP32
mode, as guarded by the predicate "SYM_32" and also for a submode of
-LP64 where symbols are assumed to be 32 bits wide. A similar
-multiclass for MIPS64 in LP64 mode is also defined:
-
- // lib/Target/Mips/Mips64InstrInfo.td
- multiclass MipsHighestHigherHiLoRelocs<Instruction Lui,
- Instruction Daddiu> {
- ...
- def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
- (Lui tglobaladdr:$in)>;
- ...
- def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
- (Daddiu ZERO_64, tglobaladdr:$in)>;
- ...
- def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
- ...
- def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
- ...
- def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
- (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
- }
-
-and it is instantiated twice:
-
- // lib/Target/Mips/Mips64InstrInfo.td
- defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
- // lib/Target/Mips/MicroMips64r6InstrInfo.td
- defm : MipsHighestHigherHiLoRelocs<LUi64, DADDIU_MM64R6>, SYM_64,
- ISA_MICROMIPS64R6;
-
-These patterns are used during instruction selection to match
-MipsISD::{Highest, Higher, Hi, Lo} to a specific machine instruction
-and operands.
+LP64 where symbols are assumed to be 32 bits wide.
More details on how multiclasses in TableGen work can be found in the
section "Multiclass definitions and instances" in the document
Removed: llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll?rev=320349&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \
-; RUN: -relocation-model=pic -O3 < %s
-
-; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6.
-
- at x = global i32 65504, align 4
- at y = global i32 60929, align 4
- at .str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
-
-define i32 @main() nounwind {
-entry:
- %0 = load i32, i32* @x, align 4
- %and1 = and i32 %0, 4
- %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
- ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
-
- %1 = load i32, i32* @y, align 4
- %and2 = and i32 %1, 5
- %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
- ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2)
- ret i32 0
-}
-
-declare i32 @printf(i8*, ...)
Modified: llvm/trunk/test/CodeGen/Mips/countleading.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/countleading.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/countleading.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/countleading.ll Mon Dec 11 03:21:40 2017
@@ -5,7 +5,6 @@
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s
; Prefixes:
; ALL - All
@@ -22,8 +21,6 @@ entry:
; MIPS64-GT-R1: clz $2, $4
-; MICROMIPS64: clz $2, $4
-
%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
ret i32 %tmp1
}
@@ -40,8 +37,6 @@ entry:
; MIPS64-GT-R1: clo $2, $4
-; MICROMIPS64: clo $2, $4
-
%neg = xor i32 %X, -1
%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
ret i32 %tmp1
@@ -63,7 +58,6 @@ entry:
; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
; MIPS64-GT-R1: dclz $2, $4
-; MICROMIPS64: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
@@ -89,7 +83,6 @@ entry:
; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
; MIPS64-GT-R1: dclo $2, $4
-; MICROMIPS64: dclo $2, $4
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
Modified: llvm/trunk/test/CodeGen/Mips/fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcmp.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcmp.ll Mon Dec 11 03:21:40 2017
@@ -16,8 +16,6 @@
; RUN: -check-prefixes=ALL,MM,MM32R3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6
define i32 @false_f32(float %a, float %b) nounwind {
; ALL-LABEL: false_f32:
@@ -61,7 +59,6 @@ define i32 @oeq_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -95,7 +92,6 @@ define i32 @ogt_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -129,7 +125,6 @@ define i32 @oge_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -163,7 +158,6 @@ define i32 @olt_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -197,7 +191,6 @@ define i32 @ole_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -233,7 +226,6 @@ define i32 @one_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -270,7 +262,6 @@ define i32 @ord_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -305,7 +296,6 @@ define i32 @ueq_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -339,7 +329,6 @@ define i32 @ugt_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -373,7 +362,6 @@ define i32 @uge_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -407,7 +395,6 @@ define i32 @ult_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -441,7 +428,6 @@ define i32 @ule_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -477,7 +463,6 @@ define i32 @une_f32(float %a, float %b)
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -512,7 +497,6 @@ define i32 @uno_f32(float %a, float %b)
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -580,7 +564,6 @@ define i32 @oeq_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -614,7 +597,6 @@ define i32 @ogt_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -648,7 +630,6 @@ define i32 @oge_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -682,7 +663,6 @@ define i32 @olt_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -716,7 +696,6 @@ define i32 @ole_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -752,7 +731,6 @@ define i32 @one_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -789,7 +767,6 @@ define i32 @ord_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -824,7 +801,6 @@ define i32 @ueq_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -858,7 +834,6 @@ define i32 @ugt_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -892,7 +867,6 @@ define i32 @uge_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -926,7 +900,6 @@ define i32 @ult_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -960,7 +933,6 @@ define i32 @ule_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -996,7 +968,6 @@ define i32 @une_f64(double %a, double %b
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1
@@ -1031,7 +1002,6 @@ define i32 @uno_f64(double %a, double %b
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1
@@ -1102,18 +1072,6 @@ entry:
; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
; MM32R6-DAG: bnezc $[[T5]],
-; MM64R6-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI32_0)
-; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0)
-; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0)
-; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG: lwc1 $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]])
-; MM64R6-DAG: cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG: bnezc $[[T9]],
-
%add = fadd fast float %at, %angle
%cmp = fcmp ogt float %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
@@ -1172,18 +1130,6 @@ entry:
; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
; MM32R6-DAG: bnezc $[[T5]],
-; MM64R6-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI33_0)
-; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0)
-; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0)
-; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG: ldc1 $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]])
-; MM64R6-DAG: cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG: bnezc $[[T9]],
-
%add = fadd fast double %at, %angle
%cmp = fcmp ogt double %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll Mon Dec 11 03:21:40 2017
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM64
; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'.
@@ -122,8 +120,6 @@ entry:
; MM32: sltu $[[T1:[0-9]+]], $3, $5
; MM32: addu16 $2, $[[T0]], $[[T1]]
- ; MM64: daddu $2, $4, $5
-
%r = add i64 %a, %b
ret i64 %r
}
@@ -228,13 +224,6 @@ entry:
; MMR6: addu16 $2, $[[T16]], $[[T20]]
; MMR6: addu16 $2, $[[T20]], $[[T21]]
- ; MM64: daddu $[[T0:[0-9]+]], $4, $6
- ; MM64: daddu $3, $5, $7
- ; MM64: sltu $[[T1:[0-9]+]], $3, $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $[[T0]], $[[T3]]
-
%r = add i128 %a, %b
ret i128 %r
}
@@ -262,9 +251,6 @@ define signext i8 @add_i8_4(i8 signext %
; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
; MM32: seb $2, $[[T0]]
- ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
- ; MM64: seb $2, $[[T0]]
-
%r = add i8 4, %a
ret i8 %r
}
@@ -283,9 +269,6 @@ define signext i16 @add_i16_4(i16 signex
; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
; MM32: seh $2, $[[T0]]
- ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
- ; MM64: seh $2, $[[T0]]
-
%r = add i16 4, %a
ret i16 %r
}
@@ -299,8 +282,6 @@ define signext i32 @add_i32_4(i32 signex
; MM32: addiur2 $2, $4, 4
- ; MM64: addiur2 $2, $4, 4
-
%r = add i32 4, %a
ret i32 %r
}
@@ -319,8 +300,6 @@ define signext i64 @add_i64_4(i64 signex
; GP64: daddiu $2, $4, 4
- ; MM64: daddiu $2, $4, 4
-
%r = add i64 4, %a
ret i64 %r
}
@@ -384,12 +363,6 @@ define signext i128 @add_i128_4(i128 sig
; MMR6: move $4, $7
; MMR6: move $5, $[[T1]]
- ; MM64: daddiu $[[T0:[0-9]+]], $5, 4
- ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $4, $[[T3]]
-
%r = add i128 4, %a
ret i128 %r
}
@@ -477,8 +450,6 @@ define signext i64 @add_i64_3(i64 signex
; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5
; MM32: addu16 $2, $4, $[[T2]]
- ; MM64: daddiu $2, $4, 3
-
%r = add i64 3, %a
ret i64 %r
}
@@ -545,12 +516,6 @@ define signext i128 @add_i128_3(i128 sig
; MMR6: move $4, $[[T5]]
; MMR6: move $5, $[[T1]]
- ; MM64: daddiu $[[T0:[0-9]+]], $5, 3
- ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $4, $[[T3]]
-
%r = add i128 3, %a
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll Mon Dec 11 03:21:40 2017
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -42,8 +40,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i1 %a, %b
ret i1 %r
}
@@ -59,8 +55,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i8 %a, %b
ret i8 %r
}
@@ -76,8 +70,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i16 %a, %b
ret i16 %r
}
@@ -94,9 +86,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = and i32 %a, %b
ret i32 %r
}
@@ -115,8 +104,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: and $2, $4, $5
-
%r = and i64 %a, %b
ret i64 %r
}
@@ -146,9 +133,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: and16 $[[T3]], $7
- ; MM64: and $2, $4, $6
- ; MM64: and $3, $5, $7
-
%r = and i128 %a, %b
ret i128 %r
}
@@ -221,8 +205,6 @@ entry:
; MM32: andi16 $3, $5, 4
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 4
-
%r = and i64 4, %b
ret i64 %r
}
@@ -244,9 +226,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 4
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 4, %b
ret i128 %r
}
@@ -315,8 +294,6 @@ entry:
; MM32: andi16 $3, $5, 31
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 31
-
%r = and i64 31, %b
ret i64 %r
}
@@ -338,9 +315,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 31
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 31, %b
ret i128 %r
}
@@ -405,8 +379,6 @@ entry:
; MM32: andi16 $3, $5, 255
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 255
-
%r = and i64 255, %b
ret i64 %r
}
@@ -428,9 +400,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 255
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 255, %b
ret i128 %r
}
@@ -506,8 +475,6 @@ entry:
; MM32: andi16 $3, $5, 32768
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 32768
-
%r = and i64 32768, %b
ret i64 %r
}
@@ -529,9 +496,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 32768
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 32768, %b
ret i128 %r
}
@@ -588,8 +552,6 @@ entry:
; MM32-DAG: andi $3, $5, 65
; MM32-DAG: li16 $2, 0
- ; MM64: andi $2, $4, 65
-
%r = and i64 65, %b
ret i64 %r
}
@@ -611,9 +573,6 @@ entry:
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
- ; MM64: andi $3, $5, 65
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 65, %b
ret i128 %r
}
@@ -678,8 +637,6 @@ entry:
; MM32-DAG: andi $3, $5, 256
; MM32-DAG: li16 $2, 0
- ; MM64: andi $2, $4, 256
-
%r = and i64 256, %b
ret i64 %r
}
@@ -701,9 +658,6 @@ entry:
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
- ; MM64: andi $3, $5, 256
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 256, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lh_lhu.ll Mon Dec 11 03:21:40 2017
@@ -1,7 +1,6 @@
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s
@us = global i16 0, align 2
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Mon Dec 11 03:21:40 2017
@@ -26,8 +26,6 @@
; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
-; RUN: FileCheck %s -check-prefix=MM64R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -59,11 +57,6 @@ entry:
; 64R6: andi $[[T0]], $[[T0]], 1
; 64R6: negu $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: andi16 $[[T0]], $[[T0]], 1
- ; MM64R6: li16 $[[T1:[0-9]+]], 0
- ; MM64R6: subu16 $2, $[[T1]], $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: andi16 $[[T0]], $[[T0]], 1
; MM32: li16 $[[T1:[0-9]+]], 0
@@ -107,9 +100,6 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seb $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: seb $2, $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seb $2, $[[T0]]
@@ -151,9 +141,6 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seh $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: seh $2, $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seh $2, $[[T0]]
@@ -173,7 +160,6 @@ entry:
; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5
- ; MM64R6: mul $2, $4, $5
; MM32: mul $2, $4, $5
@@ -217,7 +203,6 @@ entry:
; 64R1-R5: mflo $2
; 64R6: dmul $2, $4, $5
- ; MM64R6: dmul $2, $4, $5
; MM32R3: multu $[[T0:[0-9]+]], $7
; MM32R3: mflo $[[T1:[0-9]+]]
@@ -261,13 +246,6 @@ entry:
; 64R6: daddu $2, $[[T1]], $[[T0]]
; 64R6-DAG: dmul $3, $5, $7
- ; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
- ; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7
- ; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
- ; MM64R6: daddu $2, $[[T1]], $[[T0]]
- ; MM64R6-DAG: dmul $3, $5, $7
-
; MM32: lw $25, %call16(__multi3)($16)
%r = mul i128 %a, %b
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll Mon Dec 11 03:21:40 2017
@@ -26,8 +26,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @not_i1(i1 signext %a) {
entry:
@@ -98,9 +96,6 @@ entry:
; MM32: not16 $2, $4
; MM32: not16 $3, $5
- ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
- ; MM64: xor $2, $4, $[[T0]]
-
%r = xor i64 %a, -1
ret i64 %r
}
@@ -123,10 +118,6 @@ entry:
; MM32: not16 $4, $6
; MM32: not16 $5, $7
- ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
- ; MM64: xor $2, $4, $[[T0]]
- ; MM64: xor $3, $5, $[[T0]]
-
%r = xor i128 %a, -1
ret i128 %r
}
@@ -138,7 +129,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i1 %b, %a
%r = xor i1 %or, -1
@@ -152,7 +142,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i8 %b, %a
%r = xor i8 %or, -1
@@ -166,7 +155,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i16 %b, %a
%r = xor i16 %or, -1
@@ -185,10 +173,6 @@ entry:
; MM32: nor $2, $5, $4
- ; MM64: or $[[T0:[0-9]+]], $5, $4
- ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0
- ; MM64: not16 $2, $[[T1]]
-
%or = or i32 %b, %a
%r = xor i32 %or, -1
ret i32 %r
@@ -207,8 +191,6 @@ entry:
; MM32: nor $2, $6, $4
; MM32: nor $3, $7, $5
- ; MM64: nor $2, $5, $4
-
%or = or i64 %b, %a
%r = xor i64 %or, -1
ret i64 %r
@@ -239,9 +221,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: nor $5, $[[T3]], $7
- ; MM64: nor $2, $6, $4
- ; MM64: nor $3, $7, $5
-
%or = or i128 %b, %a
%r = xor i128 %or, -1
ret i128 %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll Mon Dec 11 03:21:40 2017
@@ -15,8 +15,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -29,8 +27,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i1 %a, %b
ret i1 %r
}
@@ -46,8 +42,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i8 %a, %b
ret i8 %r
}
@@ -63,8 +57,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i16 %a, %b
ret i16 %r
}
@@ -82,9 +74,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: or $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = or i32 %a, %b
ret i32 %r
}
@@ -103,8 +92,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: or $2, $4, $5
-
%r = or i64 %a, %b
ret i64 %r
}
@@ -134,9 +121,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: or16 $[[T3]], $7
- ; MM64: or $2, $4, $6
- ; MM64: or $3, $5, $7
-
%r = or i128 %a, %b
ret i128 %r
}
@@ -193,8 +177,6 @@ entry:
; MM32: ori $3, $5, 4
; MM32: move $2, $4
- ; MM64: ori $2, $4, 4
-
%r = or i64 4, %b
ret i64 %r
}
@@ -218,9 +200,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 4
- ; MM64: move $2, $4
-
%r = or i128 4, %b
ret i128 %r
}
@@ -281,8 +260,6 @@ entry:
; MM32: ori $3, $5, 31
; MM32: move $2, $4
- ; MM64: ori $2, $4, 31
-
%r = or i64 31, %b
ret i64 %r
}
@@ -306,9 +283,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 31
- ; MM64: move $2, $4
-
%r = or i128 31, %b
ret i128 %r
}
@@ -373,8 +347,6 @@ entry:
; MM32: ori $3, $5, 255
; MM32: move $2, $4
- ; MM64: ori $2, $4, 255
-
%r = or i64 255, %b
ret i64 %r
}
@@ -398,9 +370,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 255
- ; MM64: move $2, $4
-
%r = or i128 255, %b
ret i128 %r
}
@@ -464,8 +433,6 @@ entry:
; MM32: ori $3, $5, 32768
; MM32: move $2, $4
- ; MM64: ori $2, $4, 32768
-
%r = or i64 32768, %b
ret i64 %r
}
@@ -489,9 +456,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 32768
- ; MM64: move $2, $4
-
%r = or i128 32768, %b
ret i128 %r
}
@@ -552,8 +516,6 @@ entry:
; MM32: ori $3, $5, 65
; MM32: move $2, $4
- ; MM64: ori $2, $4, 65
-
%r = or i64 65, %b
ret i64 %r
}
@@ -577,9 +539,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 65
- ; MM64: move $2, $4
-
%r = or i128 65, %b
ret i128 %r
}
@@ -636,8 +595,6 @@ entry:
; MM32: ori $3, $5, 256
; MM32: move $2, $4
- ; MM64: ori $2, $4, 256
-
%r = or i64 256, %b
ret i64 %r
}
@@ -661,9 +618,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 256
- ; MM64: move $2, $4
-
%r = or i128 256, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll Mon Dec 11 03:21:40 2017
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -174,9 +172,6 @@ entry:
; MM32: lw $25, %call16(__divdi3)($2)
- ; MM64: ddiv $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = sdiv i64 %a, %b
ret i64 %r
}
@@ -192,8 +187,6 @@ entry:
; MM32: lw $25, %call16(__divti3)($16)
- ; MM64: ld $25, %call16(__divti3)($2)
-
%r = sdiv i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll Mon Dec 11 03:21:40 2017
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -166,9 +164,6 @@ entry:
; MM32: lw $25, %call16(__moddi3)($2)
- ; MM64: dmod $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = srem i64 %a, %b
ret i64 %r
}
@@ -184,8 +179,6 @@ entry:
; MM32: lw $25, %call16(__modti3)($16)
- ; MM64: ld $25, %call16(__modti3)($2)
-
%r = srem i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll Mon Dec 11 03:21:40 2017
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=GP64,MM64
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -213,16 +211,6 @@ entry:
; GP64-R2: dsubu $2, $1, $[[T1]]
; GP64-R2: dsubu $3, $5, $7
-; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the
-; dext instruction which should be used here.
-
-; MM64: dsubu $[[T0:[0-9]+]], $4, $6
-; MM64: sltu $[[T1:[0-9]+]], $5, $7
-; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
-; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
-; MM64: dsubu $2, $[[T0]], $[[T3]]
-; MM64: dsubu $3, $5, $7
-
%r = sub i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll Mon Dec 11 03:21:40 2017
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
entry:
@@ -136,9 +134,6 @@ entry:
; MM32: lw $25, %call16(__udivdi3)($2)
- ; MM64: ddivu $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = udiv i64 %a, %b
ret i64 %r
}
@@ -154,8 +149,6 @@ entry:
; MM32: lw $25, %call16(__udivti3)($16)
- ; MM64: ld $25, %call16(__udivti3)($2)
-
%r = udiv i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll Mon Dec 11 03:21:40 2017
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -192,9 +190,6 @@ entry:
; MM32: lw $25, %call16(__umoddi3)($2)
- ; MM64: dmodu $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = urem i64 %a, %b
ret i64 %r
}
@@ -210,8 +205,6 @@ entry:
; MM32: lw $25, %call16(__umodti3)($16)
- ; MM64: ld $25, %call16(__umodti3)($2)
-
%r = urem i128 %a, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll Mon Dec 11 03:21:40 2017
@@ -26,8 +26,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -40,8 +38,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i1 %a, %b
ret i1 %r
}
@@ -57,8 +53,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i8 %a, %b
ret i8 %r
}
@@ -74,8 +68,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i16 %a, %b
ret i16 %r
}
@@ -92,9 +84,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = xor i32 %a, %b
ret i32 %r
}
@@ -113,8 +102,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: xor $2, $4, $5
-
%r = xor i64 %a, %b
ret i64 %r
}
@@ -144,9 +131,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: xor16 $[[T3]], $7
- ; MM64: xor $2, $4, $6
- ; MM64: xor $3, $5, $7
-
%r = xor i128 %a, %b
ret i128 %r
}
@@ -203,8 +187,6 @@ entry:
; MM32: xori $3, $5, 4
; MM32: move $2, $4
- ; MM64: xori $2, $4, 4
-
%r = xor i64 4, %b
ret i64 %r
}
@@ -228,9 +210,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: xori $3, $5, 4
- ; MM64: move $2, $4
-
%r = xor i128 4, %b
ret i128 %r
}
Modified: llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll Mon Dec 11 03:21:40 2017
@@ -1,7 +1,5 @@
; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
-; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \
-; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; The purpose of this test is to check whether the CodeGen selects
; LW16 instruction with the base register in a range of $2-$7, $16, $17.
Modified: llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-lwc1-swc1.ll Mon Dec 11 03:21:40 2017
@@ -4,9 +4,6 @@
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
; RUN: -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,MM32
-; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
-; RUN: -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefixes=ALL,MM64
@gf0 = external global float
@@ -19,12 +16,6 @@ entry:
; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
; MM32: lwc1 $f0, 0($[[R3]])
-; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
-; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
-; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
-; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64: lwc1 $f0, 0($[[R3]])
-
%0 = load float, float* @gf0, align 4
ret float %0
}
@@ -38,12 +29,6 @@ entry:
; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
; MM32: swc1 $f12, 0($[[R3]])
-; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
-; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25
-; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
-; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64: swc1 $f12, 0($[[R3]])
-
store float %a, float* @gf0, align 4
ret void
}
Added: llvm/trunk/test/CodeGen/Mips/micromips64r6-unsupported.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips64r6-unsupported.ll?rev=320350&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips64r6-unsupported.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips64r6-unsupported.ll Mon Dec 11 03:21:40 2017
@@ -0,0 +1,5 @@
+; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s
+
+; Test that microMIPS64R6 is not supported.
+
+; CHECK: LLVM ERROR: microMIPS64R6 is not supported
Modified: llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64fpldst.ll Mon Dec 11 03:21:40 2017
@@ -2,8 +2,6 @@
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8
Modified: llvm/trunk/test/CodeGen/Mips/mips64shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64shift.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64shift.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64shift.ll Mon Dec 11 03:21:40 2017
@@ -1,5 +1,4 @@
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll Mon Dec 11 03:21:40 2017
@@ -28,10 +28,6 @@
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
-; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
-; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
-; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
-; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
@@ -169,7 +165,6 @@ entry:
; STATIC32MMR6: bc
; PIC64: jr $25
; PIC64R6: jrc $25
-; PIC64R6MM: jrc $25
; STATIC64: j
; PIC16: jalrc
Added: llvm/trunk/test/MC/Mips/micromips64r6-unsupported.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6-unsupported.s?rev=320350&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6-unsupported.s (added)
+++ llvm/trunk/test/MC/Mips/micromips64r6-unsupported.s Mon Dec 11 03:21:40 2017
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mattr=+micromips \
+# RUN: -mcpu=mips64r6 %s 2>&1 | FileCheck %s -check-prefix=CHECK-OPTION
+# RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \
+# RUN: %s 2>&1 | FileCheck %s -check-prefix=CHECK-MM-DIRECTIVE
+# RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux \
+# RUN: %s 2>&1 | FileCheck %s -check-prefix=CHECK-DIRECTIVE
+
+# CHECK-OPTION: LLVM ERROR: microMIPS64R6 is not supported
+
+.set micromips
+# CHECK-MM-DIRECTIVE: :[[@LINE-1]]:6: error: .set micromips directive is not supported with MIPS64R6
+
+.set mips64r6
+.set arch=mips64r6
+# CHECK-DIRECTIVE: :[[@LINE-2]]:6: error: MIPS64R6 is not supported with microMIPS
+# CHECK-DIRECTIVE: :[[@LINE-2]]:19: error: mips64r6 does not support microMIPS
Modified: llvm/trunk/test/MC/Mips/mips64extins.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64extins.s?rev=320350&r1=320349&r2=320350&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64extins.s (original)
+++ llvm/trunk/test/MC/Mips/mips64extins.s Mon Dec 11 03:21:40 2017
@@ -1,13 +1,8 @@
# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
# RUN: | llvm-objdump -disassemble - | FileCheck --check-prefix=OBJ %s
-# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r6 -mattr=+micromips \
-# RUN: -target-abi=n64 %s -o - | llvm-objdump -disassemble - \
-# RUN: | FileCheck --check-prefix=OBJ %s
# RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
# RUN: | FileCheck --check-prefix=ASM %s
-# RUN: llvm-mc -arch=mips64el -mcpu=mips64r6 -mattr=+micromips -target-abi=n64 \
-# RUN: %s -o - | FileCheck --check-prefix=ASM %s
dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
dextu $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
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