[llvm] r320352 - [ARM GlobalISel] Add tests for PKHBT and PKHTB
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 11 03:44:23 PST 2017
Author: rovka
Date: Mon Dec 11 03:44:23 2017
New Revision: 320352
URL: http://llvm.org/viewvc/llvm-project?rev=320352&view=rev
Log:
[ARM GlobalISel] Add tests for PKHBT and PKHTB
Test (some of) the patterns for selecting PKHBT and PKHTB. The others
are just very similar to the ones we're testing and there would be
little value in covering them as well.
Modified:
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir?rev=320352&r1=320351&r2=320352&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir Mon Dec 11 03:44:23 2017
@@ -20,6 +20,14 @@
define void @test_bicri_commutative_and() { ret void }
define void @test_bicri_commutative_both() { ret void }
+ define void @test_pkhbt() #0 { ret void }
+ define void @test_pkhbt_commutative() #0 { ret void }
+ define void @test_pkhbt_imm16_31() #0 { ret void }
+ define void @test_pkhbt_unshifted() #0 { ret void }
+
+ define void @test_pkhtb_imm16() #0 { ret void }
+ define void @test_pkhtb_imm1_15() #0 { ret void }
+
attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="-v6" }
attributes #2 = { "target-features"="+v6t2" }
@@ -576,5 +584,251 @@ body: |
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhbt
+# CHECK-LABEL: name: test_pkhbt
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 7
+ %5(s32) = G_SHL %1, %4
+ %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %7(s32) = G_AND %5, %6
+
+ %8(s32) = G_OR %3, %7
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+
+ %r0 = COPY %8(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhbt_commutative
+# CHECK-LABEL: name: test_pkhbt_commutative
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 7
+ %5(s32) = G_SHL %1, %4
+ %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %7(s32) = G_AND %5, %6
+
+ %8(s32) = G_OR %7, %3
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+
+ %r0 = COPY %8(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhbt_imm16_31
+# CHECK-LABEL: name: test_pkhbt_imm16_31
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 17
+ %5(s32) = G_SHL %1, %4
+
+ %6(s32) = G_OR %3, %5
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, %noreg
+
+ %r0 = COPY %6(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhbt_unshifted
+# CHECK-LABEL: name: test_pkhbt_unshifted
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %5(s32) = G_AND %1, %4
+
+ %6(s32) = G_OR %3, %5
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, %noreg
+
+ %r0 = COPY %6(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhtb_imm16
+# CHECK-LABEL: name: test_pkhtb_imm16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 16
+ %5(s32) = G_LSHR %1, %4
+
+ %6(s32) = G_OR %3, %5
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, %noreg
+
+ %r0 = COPY %6(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
+ ; CHECK: BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_pkhtb_imm1_15
+# CHECK-LABEL: name: test_pkhtb_imm1_15
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+
+ %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %3(s32) = G_AND %0, %2
+
+ %4(s32) = G_CONSTANT i32 7
+ %5(s32) = G_LSHR %1, %4
+ %6(s32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %7(s32) = G_AND %5, %6
+
+ %8(s32) = G_OR %3, %7
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, %noreg
+
+ %r0 = COPY %8(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
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