[llvm] r320316 - [X86] Fix a few instructions that were named Z512 instead of just Z.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 10 09:42:40 PST 2017
Author: ctopper
Date: Sun Dec 10 09:42:39 2017
New Revision: 320316
URL: http://llvm.org/viewvc/llvm-project?rev=320316&view=rev
Log:
[X86] Fix a few instructions that were named Z512 instead of just Z.
This makes things consistent with our normal instruction naming.
Modified:
llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=320316&r1=320315&r2=320316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Sun Dec 10 09:42:39 2017
@@ -583,12 +583,12 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSLLDQYri:
case X86::VPSLLDQZ128rr:
case X86::VPSLLDQZ256rr:
- case X86::VPSLLDQZ512rr:
+ case X86::VPSLLDQZrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
LLVM_FALLTHROUGH;
case X86::VPSLLDQZ128rm:
case X86::VPSLLDQZ256rm:
- case X86::VPSLLDQZ512rm:
+ case X86::VPSLLDQZrm:
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
@@ -601,12 +601,12 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSRLDQYri:
case X86::VPSRLDQZ128rr:
case X86::VPSRLDQZ256rr:
- case X86::VPSRLDQZ512rr:
+ case X86::VPSRLDQZrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
LLVM_FALLTHROUGH;
case X86::VPSRLDQZ128rm:
case X86::VPSRLDQZ256rm:
- case X86::VPSRLDQZ512rm:
+ case X86::VPSRLDQZrm:
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=320316&r1=320315&r2=320316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Dec 10 09:42:39 2017
@@ -9917,8 +9917,8 @@ multiclass avx512_shift_packed_all<bits<
Format MRMm, string OpcodeStr,
OpndItins itins, Predicate prd>{
let Predicates = [prd] in
- defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
- OpcodeStr, itins, v64i8_info>, EVEX_V512;
+ defm Z : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
+ OpcodeStr, itins, v64i8_info>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
OpcodeStr, itins, v32i8x_info>, EVEX_V256;
@@ -9958,8 +9958,8 @@ multiclass avx512_psadbw_packed_all<bits
string OpcodeStr, OpndItins itins,
Predicate prd> {
let Predicates = [prd] in
- defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v8i64_info,
- v64i8_info>, EVEX_V512;
+ defm Z : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v8i64_info,
+ v64i8_info>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v4i64x_info,
v32i8x_info>, EVEX_V256;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=320316&r1=320315&r2=320316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Dec 10 09:42:39 2017
@@ -977,14 +977,14 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 },
{ X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 },
{ X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 },
- { X86::VPSLLDQZ512rr, X86::VPSLLDQZ512rm, 0 },
+ { X86::VPSLLDQZrr, X86::VPSLLDQZrm, 0 },
{ X86::VPSLLDZri, X86::VPSLLDZmi, 0 },
{ X86::VPSLLQZri, X86::VPSLLQZmi, 0 },
{ X86::VPSLLWZri, X86::VPSLLWZmi, 0 },
{ X86::VPSRADZri, X86::VPSRADZmi, 0 },
{ X86::VPSRAQZri, X86::VPSRAQZmi, 0 },
{ X86::VPSRAWZri, X86::VPSRAWZmi, 0 },
- { X86::VPSRLDQZ512rr, X86::VPSRLDQZ512rm, 0 },
+ { X86::VPSRLDQZrr, X86::VPSRLDQZrm, 0 },
{ X86::VPSRLDZri, X86::VPSRLDZmi, 0 },
{ X86::VPSRLQZri, X86::VPSRLQZmi, 0 },
{ X86::VPSRLWZri, X86::VPSRLWZmi, 0 },
@@ -2042,7 +2042,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
{ X86::VPORDZrr, X86::VPORDZrm, 0 },
{ X86::VPORQZrr, X86::VPORQZrm, 0 },
- { X86::VPSADBWZ512rr, X86::VPSADBWZ512rm, 0 },
+ { X86::VPSADBWZrr, X86::VPSADBWZrm, 0 },
{ X86::VPSHUFBZrr, X86::VPSHUFBZrm, 0 },
{ X86::VPSLLDZrr, X86::VPSLLDZrm, 0 },
{ X86::VPSLLQZrr, X86::VPSLLQZrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=320316&r1=320315&r2=320316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Dec 10 09:42:39 2017
@@ -587,12 +587,12 @@ def: InstRW<[SKXWriteResGroup3], (instre
def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQYri")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQZ256rr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQZ512rr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSLLDQri")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQYri")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQZ256rr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQZ512rr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPSRLDQri")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPUNPCKHBWYrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "VPUNPCKHBWZ128rr(b?)(k?)(z?)")>;
@@ -4460,9 +4460,9 @@ def: InstRW<[SKXWriteResGroup119], (inst
def: InstRW<[SKXWriteResGroup119], (instregex "VPSHUFLWZ256mi(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPSHUFLWZmi(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPSLLDQZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup119], (instregex "VPSLLDQZ512rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup119], (instregex "VPSLLDQZrm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPSRLDQZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup119], (instregex "VPSRLDQZ512rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup119], (instregex "VPSRLDQZrm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPUNPCKHBWYrm")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPUNPCKHBWZ256rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup119], (instregex "VPUNPCKHBWZrm(b?)(k?)(z?)")>;
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