[PATCH] D40807: [RISCV] Support stack frames and offsets up to 32-bits

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: lib/Target/RISCV/RISCVFrameLowering.cpp:71
+
+  if (isInt<12>(Val)) {
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
----------------
reames wrote:
> You could add a case for when Val == 0 and use a reg move.
> 
> Hm, reviewing the ISA doc, it doesn't look like there's a register register move?  Ok, add is fine.  :)
Correct, there is an assembler pseudoinstruction but `mv rd, rs` is just `addi rd, rs, 0`.


================
Comment at: lib/Target/RISCV/RISCVFrameLowering.cpp:91
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), ScratchReg)
+        .addReg(ScratchReg, RegState::Kill)
+        .addImm(Lo12)
----------------
reames wrote:
> Is it correct to indicate a kill on a use when we're updating the same scratch reg?
I believe so, or at least there seem to be a number of examples of the same thing within `lib/Target/*`.


https://reviews.llvm.org/D40807