[llvm] r320303 - [X86] Flag SLM scheduler model as complete

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Dec 10 04:36:29 2017
New Revision: 320303

URL: http://llvm.org/viewvc/llvm-project?rev=320303&view=rev
Log:
[X86] Flag SLM scheduler model as complete

We just have to locally tag COPY as WriteMove

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleSLM.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=320303&r1=320302&r2=320303&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sun Dec 10 04:36:29 2017
@@ -23,16 +23,11 @@ def SLMModel : SchedMachineModel {
 
   // For small loops, expand by a small factor to hide the backedge cost.
   let LoopMicroOpBufferSize = 10;
-
-  // FIXME: SSE4 is unimplemented. This flag is set to allow
-  // the scheduler to assign a default model to unrecognized opcodes.
-  let CompleteModel = 0;
 }
 
 let SchedModel = SLMModel in {
 
 // Silvermont has 5 reservation stations for micro-ops
-
 def IEC_RSV0 : ProcResource<1>;
 def IEC_RSV1 : ProcResource<1>;
 def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
@@ -78,6 +73,9 @@ def : WriteRes<WriteLoad,  [MEC_RSV]> {
 def : WriteRes<WriteMove,  [IEC_RSV01]>;
 def : WriteRes<WriteZero,  []>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 defm : SMWriteResPair<WriteALU,   IEC_RSV01, 1>;
 defm : SMWriteResPair<WriteIMul,  IEC_RSV1,  3>;
 defm : SMWriteResPair<WriteShift, IEC_RSV0,  1>;