[llvm] r320292 - [X86] Add IN16/OUT16 to scheduling information for Haswell, Broadwell, Skylake

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Dec 10 01:14:41 2017
New Revision: 320292

URL: http://llvm.org/viewvc/llvm-project?rev=320292&view=rev
Log:
[X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake

Sandy Bridge is also missing it, but it has other issues. See PR35590.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
    llvm/trunk/lib/Target/X86/X86SchedHaswell.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=320292&r1=320291&r2=320292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Dec 10 01:14:41 2017
@@ -3990,8 +3990,8 @@ def BWWriteResGroup191 : SchedWriteRes<[
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[BWWriteResGroup191], (instregex "IN32ri")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN32rr")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)ri")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)rr")>;
 def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;
 def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;
 
@@ -4008,8 +4008,8 @@ def BWWriteResGroup194 : SchedWriteRes<[
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32ir")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32rr")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)ir")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)rr")>;
 def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;
 def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;
 

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=320292&r1=320291&r2=320292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Dec 10 01:14:41 2017
@@ -4391,8 +4391,8 @@ def HWWriteResGroup170 : SchedWriteRes<[
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[HWWriteResGroup170], (instregex "IN32ri")>;
-def: InstRW<[HWWriteResGroup170], (instregex "IN32rr")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)ri")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)rr")>;
 def: InstRW<[HWWriteResGroup170], (instregex "IN8ri")>;
 def: InstRW<[HWWriteResGroup170], (instregex "IN8rr")>;
 
@@ -4401,8 +4401,8 @@ def HWWriteResGroup171 : SchedWriteRes<[
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32ir")>;
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32rr")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)ir")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)rr")>;
 def: InstRW<[HWWriteResGroup171], (instregex "OUT8ir")>;
 def: InstRW<[HWWriteResGroup171], (instregex "OUT8rr")>;
 

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=320292&r1=320291&r2=320292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Dec 10 01:14:41 2017
@@ -4099,8 +4099,8 @@ def SKLWriteResGroup209 : SchedWriteRes<
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32ri")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32rr")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)rr")>;
 def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;
 def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;
 
@@ -4109,8 +4109,8 @@ def SKLWriteResGroup210 : SchedWriteRes<
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32ir")>;
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32rr")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)rr")>;
 def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;
 def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;
 

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=320292&r1=320291&r2=320292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Dec 10 01:14:41 2017
@@ -6801,8 +6801,8 @@ def SKXWriteResGroup247 : SchedWriteRes<
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32ri")>;
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32rr")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)rr")>;
 def: InstRW<[SKXWriteResGroup247], (instregex "IN8ri")>;
 def: InstRW<[SKXWriteResGroup247], (instregex "IN8rr")>;
 
@@ -6811,8 +6811,8 @@ def SKXWriteResGroup248 : SchedWriteRes<
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32ir")>;
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32rr")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)rr")>;
 def: InstRW<[SKXWriteResGroup248], (instregex "OUT8ir")>;
 def: InstRW<[SKXWriteResGroup248], (instregex "OUT8rr")>;