[lld] r320286 - PPC32: Support R_PPC_PLTREL32 in static mode.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 10 00:42:34 PST 2017
Author: tnorthover
Date: Sun Dec 10 00:42:34 2017
New Revision: 320286
URL: http://llvm.org/viewvc/llvm-project?rev=320286&view=rev
Log:
PPC32: Support R_PPC_PLTREL32 in static mode.
See https://reviews.llvm.org/D39226
Patch by vit9696 <vit9696 at avp.su>
Modified:
lld/trunk/ELF/Arch/PPC.cpp
lld/trunk/test/ELF/ppc-relocs.s
Modified: lld/trunk/ELF/Arch/PPC.cpp
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/ELF/Arch/PPC.cpp?rev=320286&r1=320285&r2=320286&view=diff
==============================================================================
--- lld/trunk/ELF/Arch/PPC.cpp (original)
+++ lld/trunk/ELF/Arch/PPC.cpp Sun Dec 10 00:42:34 2017
@@ -34,6 +34,15 @@ RelExpr PPC::getRelExpr(RelType Type, co
case R_PPC_REL24:
case R_PPC_REL32:
return R_PC;
+ // In general case R_PPC_PLTREL24 should result in R_PLT_PC, however, since
+ // PLT support is currently not available for PPC32 this workaround at least
+ // allows lld to resolve local symbols when performing static linkage after
+ // LLVM started to forcibly use PLT relocations by default (see D38554).
+ // Non-local symbols will need a full PLT implementation, but once it lands
+ // local symbols should still avoid PLT table with static relocation model.
+ // This is the optimisation that bfd and gold are doing by default as well.
+ case R_PPC_PLTREL24:
+ return R_PC;
default:
return R_ABS;
}
@@ -54,6 +63,7 @@ void PPC::relocateOne(uint8_t *Loc, RelT
case R_PPC_REL32:
write32be(Loc, Val);
break;
+ case R_PPC_PLTREL24:
case R_PPC_REL24:
write32be(Loc, read32be(Loc) | (Val & 0x3FFFFFC));
break;
Modified: lld/trunk/test/ELF/ppc-relocs.s
URL: http://llvm.org/viewvc/llvm-project/lld/trunk/test/ELF/ppc-relocs.s?rev=320286&r1=320285&r2=320286&view=diff
==============================================================================
--- lld/trunk/test/ELF/ppc-relocs.s (original)
+++ lld/trunk/test/ELF/ppc-relocs.s Sun Dec 10 00:42:34 2017
@@ -76,3 +76,15 @@ mystr:
# CHECK: Disassembly of section .R_PPC_ADDR32:
# CHECK: .FR_PPC_ADDR32:
# CHECK: 11024: 00 01 10 28
+
+.align 2
+.section .R_PPC_PLTREL24,"ax", at progbits
+.globl .R_PPC_PLTREL24
+.FR_PPC_PLTREL24:
+ b .Lfoox4 at PLT
+.section .R_PPC_PLTREL24_2,"ax", at progbits
+.Lfoox4:
+
+# CHECK: Disassembly of section .R_PPC_PLTREL24:
+# CHECK: .R_PPC_PLTREL24:
+# CHECK: 11028: 48 00 00 04 b .+4
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