[llvm] r320266 - [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Dec  9 13:27:03 2017
New Revision: 320266

URL: http://llvm.org/viewvc/llvm-project?rev=320266&view=rev
Log:
[X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=320266&r1=320265&r2=320266&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Dec  9 13:27:03 2017
@@ -2036,19 +2036,23 @@ def CMPXCHG16B : RI<0xC7, MRM1m, (outs),
 
 
 // Lock instruction prefix
+let SchedRW = [WriteMicrocoded] in
 def LOCK_PREFIX : I<0xF0, RawFrm, (outs),  (ins), "lock", []>;
 
+let SchedRW = [WriteNop] in {
+
 // Rex64 instruction prefix
-def REX64_PREFIX : I<0x48, RawFrm, (outs),  (ins), "rex64", []>,
+def REX64_PREFIX : I<0x48, RawFrm, (outs),  (ins), "rex64", [], IIC_NOP>,
                      Requires<[In64BitMode]>;
 
 // Data16 instruction prefix
-def DATA16_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data16", []>,
+def DATA16_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data16", [], IIC_NOP>,
                      Requires<[Not16BitMode]>;
 
 // Data instruction prefix
-def DATA32_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data32", []>,
+def DATA32_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data32", [], IIC_NOP>,
                      Requires<[In16BitMode]>;
+} // SchedRW
 
 // Repeat string operation instruction prefixes
 // These use the DF flag in the EFLAGS register to inc or dec ECX