[llvm] r320193 - [X86] CMOV pseudo instructions shouldn't need scheduling info as they should be lowered early

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Dec  8 12:42:35 2017
New Revision: 320193

URL: http://llvm.org/viewvc/llvm-project?rev=320193&view=rev
Log:
[X86] CMOV pseudo instructions shouldn't need scheduling info as they should be lowered early

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=320193&r1=320192&r2=320193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Fri Dec  8 12:42:35 2017
@@ -540,7 +540,7 @@ multiclass CMOVrr_PSEUDO<RegisterClass R
                                                 EFLAGS)))]>;
 }
 
-let usesCustomInserter = 1, Uses = [EFLAGS] in {
+let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
   // X86 doesn't have 8-bit conditional moves. Use a customInserter to
   // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
   // however that requires promoting the operands, and can induce additional
@@ -578,7 +578,7 @@ let usesCustomInserter = 1, Uses = [EFLA
   defm _V16I1  : CMOVrr_PSEUDO<VK16, v16i1>;
   defm _V32I1  : CMOVrr_PSEUDO<VK32, v32i1>;
   defm _V64I1  : CMOVrr_PSEUDO<VK64, v64i1>;
-} // usesCustomInserter = 1, Uses = [EFLAGS]
+} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]
 
 //===----------------------------------------------------------------------===//
 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions