[llvm] r320177 - [X86][MPX] Tag TSX/HLE/SGX instructions scheduler classes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Dec  8 11:26:22 2017
New Revision: 320177

URL: http://llvm.org/viewvc/llvm-project?rev=320177&view=rev
Log:
[X86][MPX] Tag TSX/HLE/SGX instructions scheduler classes

Currently tagged these as system instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSGX.td
    llvm/trunk/lib/Target/X86/X86InstrTSX.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSGX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSGX.td?rev=320177&r1=320176&r2=320177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSGX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSGX.td Fri Dec  8 11:26:22 2017
@@ -15,6 +15,7 @@
 //===----------------------------------------------------------------------===//
 // SGX instructions
 
+let SchedRW = [WriteSystem] in {
 // ENCLS - Execute an Enclave System Function of Specified Leaf Number
 def ENCLS : I<0x01, MRM_CF, (outs), (ins),
              "encls", []>, TB;
@@ -22,3 +23,4 @@ def ENCLS : I<0x01, MRM_CF, (outs), (ins
 // ENCLU - Execute an Enclave User Function of Specified Leaf Number
 def ENCLU : I<0x01, MRM_D7, (outs), (ins),
              "enclu", []>, TB;
+} // SchedRW

Modified: llvm/trunk/lib/Target/X86/X86InstrTSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrTSX.td?rev=320177&r1=320176&r2=320177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrTSX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrTSX.td Fri Dec  8 11:26:22 2017
@@ -18,6 +18,8 @@
 def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
                      [SDNPHasChain, SDNPSideEffect]>;
 
+let SchedRW = [WriteSystem] in {
+
 let usesCustomInserter = 1 in
 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
                "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
@@ -45,11 +47,14 @@ def XTEST : I<0x01, MRM_D6, (outs), (ins
 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
                  "xabort\t$imm",
                  [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
+} // SchedRW
 
 // HLE prefixes
+let SchedRW = [WriteSystem] in {
 
 let isAsmParserOnly = 1 in {
 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>;
 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>;
 }
 
+} // SchedRW