[llvm] r320169 - [X86] Tag move immediate instructions scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 8 10:35:41 PST 2017
Author: rksimon
Date: Fri Dec 8 10:35:40 2017
New Revision: 320169
URL: http://llvm.org/viewvc/llvm-project?rev=320169&view=rev
Log:
[X86] Tag move immediate instructions scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=320169&r1=320168&r2=320169&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Fri Dec 8 10:35:40 2017
@@ -284,37 +284,40 @@ def : Pat<(i64 0), (SUBREG_TO_REG (i64 0
let Predicates = [OptForSize, Not64BitMode],
AddedComplexity = 10 in {
+ let SchedRW = [WriteALU] in {
// Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,
// which only require 3 bytes compared to MOV32ri which requires 5.
let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
- [(set GR32:$dst, 1)]>;
+ [(set GR32:$dst, 1)], IIC_ALU_NONMEM>;
def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
- [(set GR32:$dst, -1)]>;
+ [(set GR32:$dst, -1)], IIC_ALU_NONMEM>;
}
+ } // SchedRW
// MOV16ri is 4 bytes, so the instructions above are smaller.
def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
}
-let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5 in {
+let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5,
+ SchedRW = [WriteALU] in {
// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
-// FIXME: Add itinerary class and Schedule.
def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
- [(set GR32:$dst, i32immSExt8:$src)]>,
- Requires<[OptForMinSize, NotWin64WithoutFP]>;
+ [(set GR32:$dst, i32immSExt8:$src)], IIC_ALU_NONMEM>,
+ Requires<[OptForMinSize, NotWin64WithoutFP]>;
def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
- [(set GR64:$dst, i64immSExt8:$src)]>,
- Requires<[OptForMinSize, NotWin64WithoutFP]>;
+ [(set GR64:$dst, i64immSExt8:$src)], IIC_ALU_NONMEM>,
+ Requires<[OptForMinSize, NotWin64WithoutFP]>;
}
// Materialize i64 constant where top 32-bits are zero. This could theoretically
// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
// that would make it more difficult to rematerialize.
let isReMaterializable = 1, isAsCheapAsAMove = 1,
- isPseudo = 1, hasSideEffects = 0 in
-def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>;
+ isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteALU] in
+def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", [],
+ IIC_ALU_NONMEM>;
// This 64-bit pseudo-move can be used for both a 64-bit constant that is
// actually the zero-extension of a 32-bit constant and for labels in the
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=320169&r1=320168&r2=320169&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Dec 8 10:35:40 2017
@@ -1559,33 +1559,39 @@ def MOV32o16a : Ii16<0xA3, RawFrmMemOffs
let mayLoad = 1 in {
let Defs = [AL] in
def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
- "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
+ "movabs{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
+ AdSize64;
let Defs = [AX] in
def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
- "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
+ "movabs{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
+ OpSize16, AdSize64;
let Defs = [EAX] in
def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
- "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
- AdSize64;
+ "movabs{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
+ OpSize32, AdSize64;
let Defs = [RAX] in
def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
- "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
+ "movabs{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
+ AdSize64;
}
let mayStore = 1 in {
let Uses = [AL] in
def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst),
- "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
+ "movabs{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
+ AdSize64;
let Uses = [AX] in
def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst),
- "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
+ "movabs{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
+ OpSize16, AdSize64;
let Uses = [EAX] in
def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst),
- "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
- AdSize64;
+ "movabs{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
+ OpSize32, AdSize64;
let Uses = [RAX] in
def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst),
- "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
+ "movabs{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
+ AdSize64;
}
} // hasSideEffects = 0
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