[PATCH] D40805: [RISCV] Support for varargs

[Sameer AbuAsal via Phabricator via llvm-commits]

sabuasal added inline comments.


================
Comment at: test/CodeGen/RISCV/vararg.ll:144
+; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
+; register pair (wher the first register is even-numbered.
+
----------------
"where the first"


https://reviews.llvm.org/D40805