[PATCH] D40961: [ARM] Fix PR35481

[Momchil Velikov via Phabricator via llvm-commits]

chill created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

The issue is when restoring `LR` when there are no available low registers after popping the callee-saves and we try to find a temporary register before the pop. In the testcase, we are in front of a `pop {r7}`, however `r7` is not in the pop-friendly set (since it's used as a frame pointer), whereas the code assumes that at least one register in the `pop` is in that set.

This patch allows `r7` to be used, regardless of its use as a frame pointer, and also just falls back to using a high register if, for some reason,
we weren't able to find a suitable temporary reg among the popped ones.

Fixes https://bugs.llvm.org/show_bug.cgi?id=35481


https://reviews.llvm.org/D40961

Files:
  lib/Target/ARM/Thumb1FrameLowering.cpp
  test/CodeGen/Thumb/PR35481.ll


Index: test/CodeGen/Thumb/PR35481.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb/PR35481.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple thumbv4t-eabi    < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T
+; RUN: llc -mtriple armv8m.base-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
+; Function Attrs: nounwind
+define <4 x i32> @f() local_unnamed_addr #0 {
+entry:
+  %call = tail call i32 @h(i32 1)
+  %call1 = tail call <4 x i32> @g(i32 %call, i32 2, i32 3, i32 4)
+  ret <4 x i32> %call1
+; CHECK: ldr r7, [sp, #4]
+; CHECK-NEXT: mov lr, r7
+; CHECK-NEXT: pop {r7}
+; CHECK-NEXT: add sp, #4
+; CHECK-V47: bx lr
+; CHECK-V8M: b g
+}
+
+declare <4 x i32> @g(i32, i32, i32, i32) local_unnamed_addr
+
+declare i32 @h(i32) local_unnamed_addr
+
+attributes #0 = { "disable-tail-calls"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" }
Index: lib/Target/ARM/Thumb1FrameLowering.cpp
===================================================================
--- lib/Target/ARM/Thumb1FrameLowering.cpp
+++ lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -611,6 +611,12 @@
   unsigned TemporaryReg = 0;
   BitVector PopFriendly =
       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
+  // R7 may be used as a frame pointer, hence marked as not generally
+  // allocatable, however there's no reason to not use it as a temporary for
+  // restoring LR.
+  if (STI.useR7AsFramePointer())
+    PopFriendly.set(ARM::R7);
+
   assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
   // Rebuild the GPRs from the high registers because they are removed
   // form the GPR reg class for thumb1.
@@ -622,17 +628,20 @@
   GPRsNoLRSP.reset(ARM::PC);
   findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
 
-  // If we couldn't find a pop-friendly register, restore LR before popping the
-  // other callee-saved registers, so we can use one of them as a temporary.
+  // If we couldn't find a pop-friendly register, try restoring LR before
+  // popping the other callee-saved registers, so we could use one of them as a
+  // temporary.
   bool UseLDRSP = false;
   if (!PopReg && MBBI != MBB.begin()) {
     auto PrevMBBI = MBBI;
     PrevMBBI--;
     if (PrevMBBI->getOpcode() == ARM::tPOP) {
-      MBBI = PrevMBBI;
-      UsedRegs.stepBackward(*MBBI);
+      UsedRegs.stepBackward(*PrevMBBI);
       findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
-      UseLDRSP = true;
+      if (PopReg) {
+        MBBI = PrevMBBI;
+        UseLDRSP = true;
+      }
     }
   }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D40961.125969.patch
Type: text/x-patch
Size: 2734 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171207/2d5ba480/attachment.bin>