[llvm] r320046 - [CodeGen] Use more getMFIfAvailable

[Francis Visoiu Mistrih via llvm-commits]

Author: thegameg
Date: Thu Dec  7 06:32:15 2017
New Revision: 320046

URL: http://llvm.org/viewvc/llvm-project?rev=320046&view=rev
Log:
[CodeGen] Use more getMFIfAvailable

Modified:
    llvm/trunk/lib/CodeGen/MachineOperand.cpp

Modified: llvm/trunk/lib/CodeGen/MachineOperand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineOperand.cpp?rev=320046&r1=320045&r2=320046&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineOperand.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineOperand.cpp Thu Dec  7 06:32:15 2017
@@ -339,13 +339,9 @@ hash_code llvm::hash_value(const Machine
 static void tryToGetTargetInfo(const MachineOperand &MO,
                                const TargetRegisterInfo *&TRI,
                                const TargetIntrinsicInfo *&IntrinsicInfo) {
-  if (const MachineInstr *MI = MO.getParent()) {
-    if (const MachineBasicBlock *MBB = MI->getParent()) {
-      if (const MachineFunction *MF = MBB->getParent()) {
-        TRI = MF->getSubtarget().getRegisterInfo();
-        IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
-      }
-    }
+  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
+    TRI = MF->getSubtarget().getRegisterInfo();
+    IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
   }
 }
 
@@ -394,15 +390,11 @@ void MachineOperand::print(raw_ostream &
     }
     // Print the register class / bank.
     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-      if (const MachineInstr *MI = getParent()) {
-        if (const MachineBasicBlock *MBB = MI->getParent()) {
-          if (const MachineFunction *MF = MBB->getParent()) {
-            const MachineRegisterInfo &MRI = MF->getRegInfo();
-            if (!PrintDef || MRI.def_empty(Reg)) {
-              OS << ':';
-              OS << printRegClassOrBank(Reg, MRI, TRI);
-            }
-          }
+      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
+        const MachineRegisterInfo &MRI = MF->getRegInfo();
+        if (!PrintDef || MRI.def_empty(Reg)) {
+          OS << ':';
+          OS << printRegClassOrBank(Reg, MRI, TRI);
         }
       }
     }