[PATCH] D40003: [RISCV] MC layer support for the rest instructions of standard compress instruction set

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Hi Shiva, I think this is basically ready to merge. I notice that it's missing the compressed floating point instructions - now the the F+D extensions are added, did you want to add those?

Check the indentation in RISCVDisassembler.cpp, and please check UImm10Lsb00NonZero and SImm6 are sorted properly with respect to the other immediate types. I'd rename GPRNonX0X2 to GPRNoX0X2.


Repository:
  rL LLVM

https://reviews.llvm.org/D40003