[llvm] r320036 - [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot

[Alex Bradbury via llvm-commits]

Author: asb
Date: Thu Dec  7 04:45:05 2017
New Revision: 320036

URL: http://llvm.org/viewvc/llvm-project?rev=320036&view=rev
Log:
[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot

Simply checking for register class equality will break once additional 
register classes are added (as is done for the RVC instruction set extension).

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp?rev=320036&r1=320035&r2=320036&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp Thu Dec  7 04:45:05 2017
@@ -52,7 +52,7 @@ void RISCVInstrInfo::storeRegToStackSlot
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
     BuildMI(MBB, I, DL, get(RISCV::SW))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
@@ -70,7 +70,7 @@ void RISCVInstrInfo::loadRegFromStackSlo
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
     BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
   else
     llvm_unreachable("Can't load this register from stack slot");