[PATCH] D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Thanks Mario, this is really helpful. From a first look this looks good. With the RV32F+RV32D MC layer patches now reviewed+merged, I've gone ahead and committed the fairly straight-forward patches for RV64* MC layer support. Could you please rebase and enable the RV64I mnemonics, then I can do a more detailed review before committing?


https://reviews.llvm.org/D40902