[PATCH] D35192: [ARM] Use ADDCARRY / SUBCARRY

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

We believe there is a problem here as the generic combiner presumes we're going to use the first result (0) but actually the code is using the second (1)

  diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  index 5387a7ed73e3a3f22931f981578859f3c0b08e90..5ec4cdeaa272988ca0a97b35b993b507dddd10b6 100644
  --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  @@ -2150,7 +2150,8 @@ SDValue DAGCombiner::visitADDLike(SDValue N0, SDValue N1, SDNode *LocReference)
     }
   
     // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
  -  if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)))
  +  if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
  +      N1.getResNo() == 0)
       return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
                          N0, N1.getOperand(0), N1.getOperand(2));
   
  -- 

@efriedma, @deadalnix is our diagnostic correct?

(Kudos to @avieira who did an amazing job chasing this)


Repository:
  rL LLVM

https://reviews.llvm.org/D35192