[PATCH] D40361: [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

There are too many redundant tests. I'd keep one for each size/type on both boundaries (0, 31) and add negative tests to check that you can't zip predicate registers with data registers, register numbers out of bounds, different number of registers (2, 4), etc.


https://reviews.llvm.org/D40361