[llvm] r319878 - [X86] Split 512-bit vector extends from types other than vXi1 out of LowerZERO_EXTEND_AVX512/LowerSIGN_EXTEND_AVX512. NFCI
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 5 23:37:20 PST 2017
Author: ctopper
Date: Tue Dec 5 23:37:20 2017
New Revision: 319878
URL: http://llvm.org/viewvc/llvm-project?rev=319878&view=rev
Log:
[X86] Split 512-bit vector extends from types other than vXi1 out of LowerZERO_EXTEND_AVX512/LowerSIGN_EXTEND_AVX512. NFCI
Most of the code in these routines is for handling extends from vXi1 types. The 512-bit handling for other extends is very much like the AVX2 code. So make the special routines just do vXi1 types and move the other 512-bit handling to the place that handles AVX2.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=319878&r1=319877&r2=319878&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Dec 5 23:37:20 2017
@@ -16090,6 +16090,19 @@ static SDValue LowerAVXExtend(SDValue Op
MVT InVT = In.getSimpleValueType();
SDLoc dl(Op);
+ if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
+ (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
+ (VT != MVT::v16i16 || InVT != MVT::v16i8) &&
+ (VT != MVT::v8i64 || InVT != MVT::v8i32) &&
+ (VT != MVT::v8i64 || InVT != MVT::v8i16) &&
+ (VT != MVT::v16i32 || InVT != MVT::v16i16) &&
+ (VT != MVT::v16i32 || InVT != MVT::v16i8) &&
+ (VT != MVT::v32i16 || InVT != MVT::v32i8))
+ return SDValue();
+
+ if (Subtarget.hasInt256())
+ return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
+
// Optimize vectors in AVX mode:
//
// v8i16 -> v8i32
@@ -16103,14 +16116,6 @@ static SDValue LowerAVXExtend(SDValue Op
// Concat upper and lower parts.
//
- if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
- ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
- ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
- return SDValue();
-
- if (Subtarget.hasInt256())
- return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
-
SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
SDValue Undef = DAG.getUNDEF(InVT);
bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
@@ -16126,21 +16131,16 @@ static SDValue LowerAVXExtend(SDValue Op
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
}
-static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
- const X86Subtarget &Subtarget, SelectionDAG &DAG) {
+static SDValue LowerZERO_EXTEND_Mask(SDValue Op,
+ const X86Subtarget &Subtarget,
+ SelectionDAG &DAG) {
MVT VT = Op->getSimpleValueType(0);
SDValue In = Op->getOperand(0);
MVT InVT = In.getSimpleValueType();
+ assert(InVT.getVectorElementType() == MVT::i1 && "Unexpected input type!");
SDLoc DL(Op);
unsigned NumElts = VT.getVectorNumElements();
- if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1 &&
- (NumElts == 8 || NumElts == 16 || Subtarget.hasBWI()))
- return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
-
- if (InVT.getVectorElementType() != MVT::i1)
- return SDValue();
-
// Extend VT if the scalar type is v8/v16 and BWI is not supported.
MVT ExtVT = VT;
if (!Subtarget.hasBWI() &&
@@ -16179,12 +16179,11 @@ static SDValue LowerZERO_EXTEND_AVX512(
static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
- MVT VT = Op->getSimpleValueType(0);
SDValue In = Op->getOperand(0);
MVT InVT = In.getSimpleValueType();
- if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
- return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), VT, In);
+ if (InVT.getVectorElementType() == MVT::i1)
+ return LowerZERO_EXTEND_Mask(Op, Subtarget, DAG);
if (Subtarget.hasFp256())
if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
@@ -16199,8 +16198,8 @@ static SDValue LowerZERO_EXTEND(SDValue
SDValue In = Op.getOperand(0);
MVT SVT = In.getSimpleValueType();
- if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
- return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
+ if (SVT.getVectorElementType() == MVT::i1)
+ return LowerZERO_EXTEND_Mask(Op, Subtarget, DAG);
if (Subtarget.hasFp256())
if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
@@ -18285,28 +18284,18 @@ SDValue X86TargetLowering::LowerSELECT(S
return DAG.getNode(X86ISD::CMOV, DL, Op.getValueType(), Ops);
}
-static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
- const X86Subtarget &Subtarget,
- SelectionDAG &DAG) {
+static SDValue LowerSIGN_EXTEND_Mask(SDValue Op,
+ const X86Subtarget &Subtarget,
+ SelectionDAG &DAG) {
MVT VT = Op->getSimpleValueType(0);
SDValue In = Op->getOperand(0);
MVT InVT = In.getSimpleValueType();
+ assert(InVT.getVectorElementType() == MVT::i1 && "Unexpected input type!");
MVT VTElt = VT.getVectorElementType();
- MVT InVTElt = InVT.getVectorElementType();
SDLoc dl(Op);
unsigned NumElts = VT.getVectorNumElements();
- if (VT.is512BitVector() && InVTElt != MVT::i1 &&
- (NumElts == 8 || NumElts == 16 || Subtarget.hasBWI())) {
- if (In.getOpcode() == X86ISD::VSEXT)
- return getExtendInVec(In.getOpcode(), dl, VT, In.getOperand(0), DAG);
- return getExtendInVec(X86ISD::VSEXT, dl, VT, In, DAG);
- }
-
- if (InVTElt != MVT::i1)
- return SDValue();
-
// Extend VT if the scalar type is v8/v16 and BWI is not supported.
MVT ExtVT = VT;
if (!Subtarget.hasBWI() && VTElt.getSizeInBits() <= 16)
@@ -18441,12 +18430,17 @@ static SDValue LowerSIGN_EXTEND(SDValue
MVT InVT = In.getSimpleValueType();
SDLoc dl(Op);
- if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
- return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
+ if (InVT.getVectorElementType() == MVT::i1)
+ return LowerSIGN_EXTEND_Mask(Op, Subtarget, DAG);
- if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
- (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
- (VT != MVT::v16i16 || InVT != MVT::v16i8))
+ if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
+ (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
+ (VT != MVT::v16i16 || InVT != MVT::v16i8) &&
+ (VT != MVT::v8i64 || InVT != MVT::v8i32) &&
+ (VT != MVT::v8i64 || InVT != MVT::v8i16) &&
+ (VT != MVT::v16i32 || InVT != MVT::v16i16) &&
+ (VT != MVT::v16i32 || InVT != MVT::v16i8) &&
+ (VT != MVT::v32i16 || InVT != MVT::v32i8))
return SDValue();
if (Subtarget.hasInt256())
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