[PATCH] D40851: [AMDGPU] Improve verifier wrt vcc subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Registers vcc_lo and vcc_hi are added to the checks for constant bus
restriction. This has resulted in two test failures:

1. attr-amdgpu-num-sgpr.ll fails at instructions: %vgpr4<def> = V_MOV_B32_e32 %vcc_lo, ... %vcc<imp-use> %vgpr5<def> = V_MOV_B32_e32 %vcc_hi, ... %vcc<imp-use,kill> ...

  We were incorrectly assuming that vcc and vcc_lo uses are distinct.

2. inserted-wait-states.mir fails at the instruction:

  %vgpr4<def> = V_WRITELANE_B32 %sgpr4, %vcc_lo

  v_writelane_b32 is an exception from constant bus restriction: vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const.

Both verifier errors are fixed.


https://reviews.llvm.org/D40851

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp


Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2455,7 +2455,8 @@
     return true;
 
   // SGPRs use the constant bus
-  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
+  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::VCC_LO ||
+          MO.getReg() == AMDGPU::VCC_HI || MO.getReg() == AMDGPU::M0 ||
           (!MO.isImplicit() &&
            (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
             AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
@@ -2469,6 +2470,8 @@
 
     switch (MO.getReg()) {
     case AMDGPU::VCC:
+    case AMDGPU::VCC_LO:
+    case AMDGPU::VCC_HI:
     case AMDGPU::M0:
     case AMDGPU::FLAT_SCR:
       return MO.getReg();
@@ -2733,15 +2736,18 @@
       const MachineOperand &MO = MI.getOperand(OpIdx);
       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
         if (MO.isReg()) {
-          if (MO.getReg() != SGPRUsed)
+          if (SGPRUsed == AMDGPU::NoRegister ||
+              !RI.regsOverlap(MO.getReg(), SGPRUsed))
             ++ConstantBusCount;
           SGPRUsed = MO.getReg();
         } else {
           ++ConstantBusCount;
         }
       }
     }
-    if (ConstantBusCount > 1) {
+    // v_writelane_b32 is an exception from constant bus restriction:
+    // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
+    if (ConstantBusCount > 1 && Opcode != AMDGPU::V_WRITELANE_B32) {
       ErrInfo = "VOP* instruction uses the constant bus more than once";
       return false;
     }


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