[llvm] r319782 - [X86][AVX512] Drop some default NoItinerary arguments that aren't needed any more
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 5 08:10:57 PST 2017
Author: rksimon
Date: Tue Dec 5 08:10:57 2017
New Revision: 319782
URL: http://llvm.org/viewvc/llvm-project?rev=319782&view=rev
Log:
[X86][AVX512] Drop some default NoItinerary arguments that aren't needed any more
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319782&r1=319781&r2=319782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Dec 5 08:10:57 2017
@@ -311,7 +311,7 @@ multiclass AVX512_maskable_scalar<bits<8
dag Outs, dag Ins, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
dag RHS,
- InstrItinClass itin = NoItinerary,
+ InstrItinClass itin,
bit IsCommutable = 0> :
AVX512_maskable<O, F, _, Outs, Ins, OpcodeStr, AttSrcAsm, IntelSrcAsm,
RHS, itin, IsCommutable, 0, X86selects>;
@@ -340,7 +340,7 @@ multiclass AVX512_maskable_3src<bits<8>
multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag NonTiedIns, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
- dag RHS, InstrItinClass itin = NoItinerary,
+ dag RHS, InstrItinClass itin,
bit IsCommutable = 0,
bit IsKCommutable = 0,
bit MaskOnly = 0> :
@@ -353,7 +353,7 @@ multiclass AVX512_maskable_in_asm<bits<8
string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
list<dag> Pattern,
- InstrItinClass itin = NoItinerary> :
+ InstrItinClass itin> :
AVX512_maskable_custom<O, F, Outs, Ins,
!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
!con((ins _.KRCWM:$mask), Ins),
@@ -370,7 +370,7 @@ multiclass AVX512_maskable_custom_cmp<bi
string AttSrcAsm, string IntelSrcAsm,
list<dag> Pattern,
list<dag> MaskingPattern,
- InstrItinClass itin = NoItinerary,
+ InstrItinClass itin,
bit IsCommutable = 0> {
let isCommutable = IsCommutable in
def NAME: AVX512<O, F, Outs, Ins,
@@ -390,7 +390,7 @@ multiclass AVX512_maskable_common_cmp<bi
string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
dag RHS, dag MaskingRHS,
- InstrItinClass itin = NoItinerary,
+ InstrItinClass itin,
bit IsCommutable = 0> :
AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
AttSrcAsm, IntelSrcAsm,
@@ -400,7 +400,7 @@ multiclass AVX512_maskable_common_cmp<bi
multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag Ins, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
- dag RHS, InstrItinClass itin = NoItinerary,
+ dag RHS, InstrItinClass itin,
bit IsCommutable = 0> :
AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
!con((ins _.KRCWM:$mask), Ins),
@@ -410,7 +410,7 @@ multiclass AVX512_maskable_cmp<bits<8> O
multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag Ins, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
- InstrItinClass itin = NoItinerary> :
+ InstrItinClass itin> :
AVX512_maskable_custom_cmp<O, F, Outs,
Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
AttSrcAsm, IntelSrcAsm, [],[], itin>;
@@ -422,7 +422,7 @@ multiclass AVX512_maskable_logic<bits<8>
dag Outs, dag Ins, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
dag RHS, dag MaskedRHS,
- InstrItinClass itin = NoItinerary,
+ InstrItinClass itin,
bit IsCommutable = 0, SDNode Select = vselect> :
AVX512_maskable_custom<O, F, Outs, Ins,
!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
@@ -4770,7 +4770,8 @@ multiclass avx512_fp_scalar_sae<bits<8>
(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
"{sae}, $src2, $src1", "$src1, $src2, {sae}",
(SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
- (i32 FROUND_NO_EXC))>, EVEX_B, Sched<[itins.Sched]>;
+ (i32 FROUND_NO_EXC)), itins.rr>, EVEX_B,
+ Sched<[itins.Sched]>;
}
}
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