[llvm] r319772 - [X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 5 06:59:40 PST 2017
Author: rksimon
Date: Tue Dec 5 06:59:40 2017
New Revision: 319772
URL: http://llvm.org/viewvc/llvm-project?rev=319772&view=rev
Log:
[X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319772&r1=319771&r2=319772&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Dec 5 06:59:40 2017
@@ -6288,21 +6288,21 @@ defm VFNMSUB : avx512_fma3s<0xAF, 0xBF,
//===----------------------------------------------------------------------===//
let Constraints = "$src1 = $dst" in {
multiclass avx512_pmadd52_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
- X86VectorVTInfo _> {
+ OpndItins itins, X86VectorVTInfo _> {
// NOTE: The SDNode have the multiply operands first with the add last.
// This enables commuted load patterns to be autogenerated by tablegen.
let ExeDomain = _.ExeDomain in {
defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.RC:$src3),
OpcodeStr, "$src3, $src2", "$src2, $src3",
- (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), NoItinerary, 1, 1>,
- AVX512FMA3Base;
+ (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), itins.rr, 1, 1>,
+ AVX512FMA3Base, Sched<[itins.Sched]>;
defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.MemOp:$src3),
OpcodeStr, "$src3, $src2", "$src2, $src3",
- (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
- AVX512FMA3Base;
+ (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)),
+ itins.rm>, AVX512FMA3Base, Sched<[itins.Sched.Folded, ReadAfterLd]>;
defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.ScalarMemOp:$src3),
@@ -6310,30 +6310,30 @@ multiclass avx512_pmadd52_rm<bits<8> opc
!strconcat("$src2, ${src3}", _.BroadcastStr ),
(OpNode _.RC:$src2,
(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))),
- _.RC:$src1)>,
- AVX512FMA3Base, EVEX_B;
+ _.RC:$src1), itins.rm>,
+ AVX512FMA3Base, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
}
} // Constraints = "$src1 = $dst"
multiclass avx512_pmadd52_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
- AVX512VLVectorVTInfo _> {
+ OpndItins itins, AVX512VLVectorVTInfo _> {
let Predicates = [HasIFMA] in {
- defm Z : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info512>,
+ defm Z : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, itins, _.info512>,
EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
}
let Predicates = [HasVLX, HasIFMA] in {
- defm Z256 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info256>,
+ defm Z256 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, itins, _.info256>,
EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
- defm Z128 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, _.info128>,
+ defm Z128 : avx512_pmadd52_rm<opc, OpcodeStr, OpNode, itins, _.info128>,
EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
}
}
defm VPMADD52LUQ : avx512_pmadd52_common<0xb4, "vpmadd52luq", x86vpmadd52l,
- avx512vl_i64_info>, VEX_W;
+ SSE_PMADD, avx512vl_i64_info>, VEX_W;
defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h,
- avx512vl_i64_info>, VEX_W;
+ SSE_PMADD, avx512vl_i64_info>, VEX_W;
//===----------------------------------------------------------------------===//
// AVX-512 Scalar convert from sign integer to float/double
@@ -9848,38 +9848,41 @@ defm VPSRLDQ : avx512_shift_packed_all<0
multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
- string OpcodeStr, X86VectorVTInfo _dst,
- X86VectorVTInfo _src>{
+ string OpcodeStr, OpndItins itins,
+ X86VectorVTInfo _dst, X86VectorVTInfo _src> {
def rr : AVX512BI<opc, MRMSrcReg,
(outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set _dst.RC:$dst,(_dst.VT
(OpNode (_src.VT _src.RC:$src1),
- (_src.VT _src.RC:$src2))))]>;
+ (_src.VT _src.RC:$src2))))], itins.rr>,
+ Sched<[itins.Sched]>;
def rm : AVX512BI<opc, MRMSrcMem,
(outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set _dst.RC:$dst,(_dst.VT
(OpNode (_src.VT _src.RC:$src1),
(_src.VT (bitconvert
- (_src.LdFrag addr:$src2))))))]>;
+ (_src.LdFrag addr:$src2))))))], itins.rm>,
+ Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
- string OpcodeStr, Predicate prd> {
+ string OpcodeStr, OpndItins itins,
+ Predicate prd> {
let Predicates = [prd] in
- defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
+ defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v8i64_info,
v64i8_info>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
- defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
+ defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v4i64x_info,
v32i8x_info>, EVEX_V256;
- defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
+ defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, itins, v2i64x_info,
v16i8x_info>, EVEX_V128;
}
}
defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
- HasBWI>, EVEX_4V, VEX_WIG;
+ SSE_MPSADBW_ITINS, HasBWI>, EVEX_4V, VEX_WIG;
// Transforms to swizzle an immediate to enable better matching when
// memory operand isn't in the right place.
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