[llvm] r319767 - [X86][AVX512] Cleanup bit logic scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 5 06:04:23 PST 2017
Author: rksimon
Date: Tue Dec 5 06:04:23 2017
New Revision: 319767
URL: http://llvm.org/viewvc/llvm-project?rev=319767&view=rev
Log:
[X86][AVX512] Cleanup bit logic scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=319767&r1=319766&r2=319767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Dec 5 06:04:23 2017
@@ -4597,7 +4597,7 @@ let Predicates = [HasAVX512] in {
// be set to null_frag for 32-bit elements.
multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr,
SDPatternOperator OpNode,
- SDNode OpNodeMsk, X86VectorVTInfo _,
+ SDNode OpNodeMsk, OpndItins itins, X86VectorVTInfo _,
bit IsCommutable = 0> {
let hasSideEffects = 0 in
defm rr : AVX512_maskable_logic<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -4607,8 +4607,8 @@ multiclass avx512_logic_rm<bits<8> opc,
(bitconvert (_.VT _.RC:$src2)))),
(_.VT (bitconvert (_.i64VT (OpNodeMsk _.RC:$src1,
_.RC:$src2)))),
- IIC_SSE_BIT_P_RR, IsCommutable>,
- AVX512BIBase, EVEX_4V;
+ itins.rr, IsCommutable>, AVX512BIBase, EVEX_4V,
+ Sched<[itins.Sched]>;
let hasSideEffects = 0, mayLoad = 1 in
defm rm : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
@@ -4618,17 +4618,18 @@ multiclass avx512_logic_rm<bits<8> opc,
(bitconvert (_.LdFrag addr:$src2)))),
(_.VT (bitconvert (_.i64VT (OpNodeMsk _.RC:$src1,
(bitconvert (_.LdFrag addr:$src2)))))),
- IIC_SSE_BIT_P_RM>,
- AVX512BIBase, EVEX_4V;
+ itins.rm>, AVX512BIBase, EVEX_4V,
+ Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
// OpNodeMsk is the OpNode to use where element size is important. So use
// for all of the broadcast patterns.
multiclass avx512_logic_rmb<bits<8> opc, string OpcodeStr,
SDPatternOperator OpNode,
- SDNode OpNodeMsk, X86VectorVTInfo _,
+ SDNode OpNodeMsk, OpndItins itins, X86VectorVTInfo _,
bit IsCommutable = 0> :
- avx512_logic_rm<opc, OpcodeStr, OpNode, OpNodeMsk, _, IsCommutable> {
+ avx512_logic_rm<opc, OpcodeStr, OpNode, OpNodeMsk, itins, _,
+ IsCommutable> {
defm rmb : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
"${src2}"##_.BroadcastStr##", $src1",
@@ -4641,40 +4642,42 @@ multiclass avx512_logic_rmb<bits<8> opc,
(bitconvert
(_.VT (X86VBroadcast
(_.ScalarLdFrag addr:$src2)))))))),
- IIC_SSE_BIT_P_RM>,
- AVX512BIBase, EVEX_4V, EVEX_B;
+ itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B,
+ Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
multiclass avx512_logic_rmb_vl<bits<8> opc, string OpcodeStr,
SDPatternOperator OpNode,
- SDNode OpNodeMsk, AVX512VLVectorVTInfo VTInfo,
+ SDNode OpNodeMsk, OpndItins itins,
+ AVX512VLVectorVTInfo VTInfo,
bit IsCommutable = 0> {
let Predicates = [HasAVX512] in
- defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, VTInfo.info512,
- IsCommutable>, EVEX_V512;
+ defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
+ VTInfo.info512, IsCommutable>, EVEX_V512;
let Predicates = [HasAVX512, HasVLX] in {
- defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk,
+ defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
VTInfo.info256, IsCommutable>, EVEX_V256;
- defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk,
+ defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
VTInfo.info128, IsCommutable>, EVEX_V128;
}
}
multiclass avx512_logic_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
- SDNode OpNode, bit IsCommutable = 0> {
- defm Q : avx512_logic_rmb_vl<opc_q, OpcodeStr#"q", OpNode, OpNode,
+ SDNode OpNode, OpndItins itins,
+ bit IsCommutable = 0> {
+ defm Q : avx512_logic_rmb_vl<opc_q, OpcodeStr#"q", OpNode, OpNode, itins,
avx512vl_i64_info, IsCommutable>,
VEX_W, EVEX_CD8<64, CD8VF>;
- defm D : avx512_logic_rmb_vl<opc_d, OpcodeStr#"d", null_frag, OpNode,
+ defm D : avx512_logic_rmb_vl<opc_d, OpcodeStr#"d", null_frag, OpNode, itins,
avx512vl_i32_info, IsCommutable>,
EVEX_CD8<32, CD8VF>;
}
-defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, 1>;
-defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, 1>;
-defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, 1>;
-defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp>;
+defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, SSE_BIT_ITINS_P, 1>;
+defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, SSE_BIT_ITINS_P, 1>;
+defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, SSE_BIT_ITINS_P, 1>;
+defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp, SSE_BIT_ITINS_P>;
//===----------------------------------------------------------------------===//
// AVX-512 FP arithmetic
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=319767&r1=319766&r2=319767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Tue Dec 5 06:04:23 2017
@@ -5081,7 +5081,7 @@ define <16 x i32> @vpandd(<16 x i32> %a,
; GENERIC-LABEL: vpandd:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpandd:
@@ -5101,7 +5101,7 @@ define <16 x i32> @vpandnd(<16 x i32> %a
; GENERIC-LABEL: vpandnd:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0
+; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpandnd:
@@ -5123,7 +5123,7 @@ define <16 x i32> @vpord(<16 x i32> %a,
; GENERIC-LABEL: vpord:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpord:
@@ -5143,7 +5143,7 @@ define <16 x i32> @vpxord(<16 x i32> %a,
; GENERIC-LABEL: vpxord:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpxord:
@@ -5163,7 +5163,7 @@ define <8 x i64> @vpandq(<8 x i64> %a, <
; GENERIC-LABEL: vpandq:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpandq:
@@ -5182,7 +5182,7 @@ define <8 x i64> @vpandnq(<8 x i64> %a,
; GENERIC-LABEL: vpandnq:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0
+; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpandnq:
@@ -5202,7 +5202,7 @@ define <8 x i64> @vporq(<8 x i64> %a, <8
; GENERIC-LABEL: vporq:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vporq:
@@ -5221,7 +5221,7 @@ define <8 x i64> @vpxorq(<8 x i64> %a, <
; GENERIC-LABEL: vpxorq:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
-; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: vpxorq:
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