[PATCH] D38196: [AArch64] Avoid interleaved SIMD store instructions for Exynos

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls accepted this revision.
kristof.beyls added a comment.
This revision is now accepted and ready to land.

Thanks for your patience with my long string of review comments.
With just still addressing the few more nitpicks, I think this will have gotten to an acceptable state.



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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:73-76
+  std::map<std::pair<unsigned, std::string>, bool> SIMDInstrTable;
+  // This is used to cache the decision of whether to leave the Interleave-Store
+  // instructions replacement pass early or not for a particular target.
+  std::map<std::string, bool> InterlEarlyExit;
----------------
std::unordered_map is probably sufficient and slightly faster than std::map?


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Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:297-298
+    std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU();
+    if (!InterlEarlyExit.empty() &&
+        InterlEarlyExit.find(Subtarget) != InterlEarlyExit.end())
+      return InterlEarlyExit[Subtarget];
----------------
It seems that the !InterlEarlyExit.empty() condition is not needed here?


https://reviews.llvm.org/D38196