[PATCH] D40383: Add RISCV privileged instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Is there any reason not to include the ecall/ebreak instruction definitions in this patch? (My apologies - I should have directly asked this when commenting on the fact that ecall/ebreak tests were present but not the definitions).

For what it's worth, the R-type format is now listed in the privileged ISA description https://github.com/riscv/riscv-isa-manual/commit/9f22e9a9d7b3e3d9649fb0a9d1d0b48821037222. Switching the definitions of URET, SRET, MRET, WFI, SFENCE.VMA to use RVInstR would be slightly preferable.



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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:586
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+  def URET : Priv<"uret"> {
----------------
Along with some of the other backends, we typically treat `let Foo = ..` much like a C++ namespace declaration in terms of indentation (LLVM [guidelines](https://llvm.org/docs/CodingStandards.html#namespace-indentation)).

See RISCVInstrInfo.td for some examples.


https://reviews.llvm.org/D40383