[PATCH] D39849: [RISCV] Implement prolog and epilog insertion

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

small drive by comments.



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Comment at: lib/Target/RISCV/RISCVFrameLowering.cpp:130
+  DebugLoc DL = MBBI->getDebugLoc();
+  unsigned FPReg = RISCV::X8;
+  unsigned SPReg = RISCV::X2;
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You've got these in a couple of places, time for an alias in the enum?


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Comment at: test/CodeGen/RISCV/addc-adde-sube-subc.ll:10
 ; RV32I:       # BB#0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp)
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The test churn in this patch is really unfortunate.  Is there a small change you can add to not need all the spill code for most functions?


https://reviews.llvm.org/D39849