[PATCH] D39898: [RISCV] Add custom CC_RISCV calling convention and improved call support

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:386
+    // The second half can also be passed via register.
+    State.addLoc(
+        CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
----------------
apazos wrote:
> Maybe if you add Reg1 Reg2 vars upfront, then you can rewrite the logic in a simpler way?
> 
> if (Reg1) {
>  if (Reg2)
>   // both halves in regs
>  else
>   // first half in reg only, the other on the stack
> } else
>   // both halves on the stack
Doesn't this way require more repetition? e.g. the logic to pass the first half via registers must be replicated in case 1 and 2, and the logic to pass the second half on the stack must be replicated in case 2 and case 3.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:414
+
+  SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
+  SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
----------------
apazos wrote:
> why change the name from PendingLocs to PendingMembers?
Honestly, because all other backends accessing State.getPendingLocs name the result PendingMembers, and I assumed the name made sense to others. I don't see a good reason for the name, so I've gone ahead and used PendingLocs instead.


https://reviews.llvm.org/D39898