[PATCH] D40421: [CodeGen] Always use `printReg` to print registers in both MIR and debug output
Francis Visoiu Mistrih via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 30 08:13:18 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL319445: [CodeGen] Always use `printReg` to print registers in both MIR and debug (authored by thegameg).
Changed prior to commit:
https://reviews.llvm.org/D40421?vs=124157&id=124946#toc
Repository:
rL LLVM
https://reviews.llvm.org/D40421
Files:
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
llvm/trunk/lib/CodeGen/RegAllocFast.cpp
llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/StackMaps.cpp
llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
llvm/trunk/test/CodeGen/AArch64/machine-outliner-remarks.ll
llvm/trunk/test/CodeGen/AMDGPU/fadd.ll
llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mir
llvm/trunk/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll
llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir
llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir
llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir
llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir
llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir
llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir
llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir
llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir
llvm/trunk/test/CodeGen/ARM/indirect-hidden.ll
llvm/trunk/test/CodeGen/ARM/litpool-licm.ll
llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir
llvm/trunk/test/CodeGen/ARM/local-call.ll
llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir
llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir
llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir
llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir
llvm/trunk/test/CodeGen/ARM/pr25317.ll
llvm/trunk/test/CodeGen/ARM/preferred-align.ll
llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir
llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir
llvm/trunk/test/CodeGen/ARM/scavenging.mir
llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir
llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir
llvm/trunk/test/CodeGen/ARM/thumb-litpool.ll
llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll
llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir
llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir
llvm/trunk/test/CodeGen/Hexagon/duplex.ll
llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir
llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir
llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir
llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir
llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir
llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir
llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir
llvm/trunk/test/CodeGen/Mips/const-mult.ll
llvm/trunk/test/CodeGen/Mips/mips64signextendsesf.ll
llvm/trunk/test/CodeGen/PowerPC/cxx_tlscc64.ll
llvm/trunk/test/CodeGen/PowerPC/debuginfo-split-int.ll
llvm/trunk/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll
llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll
llvm/trunk/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
llvm/trunk/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
llvm/trunk/test/CodeGen/SystemZ/fp-cmp-07.mir
llvm/trunk/test/CodeGen/SystemZ/fp-conv-17.mir
llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
llvm/trunk/test/CodeGen/Thumb/machine-cse-physreg.mir
llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir
llvm/trunk/test/CodeGen/Thumb2/bicbfi.ll
llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-GV.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-frameIndex.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
llvm/trunk/test/CodeGen/X86/block-placement.mir
llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir
llvm/trunk/test/CodeGen/X86/domain-reassignment.mir
llvm/trunk/test/CodeGen/X86/dynamic-alloca-lifetime.ll
llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir
llvm/trunk/test/CodeGen/X86/fcmove.ll
llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir
llvm/trunk/test/CodeGen/X86/i486-fence-loop.ll
llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir
llvm/trunk/test/CodeGen/X86/ipra-inline-asm.ll
llvm/trunk/test/CodeGen/X86/ipra-reg-alias.ll
llvm/trunk/test/CodeGen/X86/ipra-reg-usage.ll
llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir
llvm/trunk/test/CodeGen/X86/leaFixup32.mir
llvm/trunk/test/CodeGen/X86/leaFixup64.mir
llvm/trunk/test/CodeGen/X86/movtopush.mir
llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir
llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir
llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir
llvm/trunk/test/CodeGen/X86/pr27681.mir
llvm/trunk/test/CodeGen/X86/pre-coalesce.mir
llvm/trunk/test/CodeGen/X86/system-intrinsics-xgetbv.ll
llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir
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