[llvm] r319331 - [ARM][DAG] Revert Disable post-legalization store merge for ARM

[Nirav Dave via llvm-commits]

Author: niravd
Date: Wed Nov 29 10:06:13 2017
New Revision: 319331

URL: http://llvm.org/viewvc/llvm-project?rev=319331&view=rev
Log:
[ARM][DAG] Revert Disable post-legalization store merge for ARM

Partially reverting enabling of post-legalization store merge
(r319036) for just ARM backend as it is causing incorrect code
in some Thumb2 cases.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
    llvm/trunk/test/CodeGen/ARM/fp16-promote.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=319331&r1=319330&r2=319331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Nov 29 10:06:13 2017
@@ -532,6 +532,9 @@ class VectorType;
     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
                                    unsigned &Cost) const override;
 
+    // Disable currently because of invalid merge.
+    bool mergeStoresAfterLegalization() const override { return false; }
+
     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
                           const SelectionDAG &DAG) const override {
       // Do not merge to larger than i32.

Modified: llvm/trunk/test/CodeGen/ARM/fp16-promote.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-promote.ll?rev=319331&r1=319330&r2=319331&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-promote.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-promote.ll Wed Nov 29 10:06:13 2017
@@ -817,37 +817,25 @@ define void @test_fmuladd(half* %p, half
 
 ; CHECK-ALL-LABEL: test_insertelement:
 ; CHECK-ALL: sub sp, sp, #8
-
-; CHECK-VFP:	and	
-; CHECK-VFP:	mov	
-; CHECK-VFP:	ldrd	
-; CHECK-VFP:	orr	
-; CHECK-VFP:	ldrh	
-; CHECK-VFP:	stm	
-; CHECK-VFP:	strh	
-; CHECK-VFP:	ldm	
-; CHECK-VFP:	stm	
-
-; CHECK-NOVFP: ldrh
-; CHECK-NOVFP: ldrh
-; CHECK-NOVFP: ldrh
-; CHECK-NOVFP: ldrh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: mov
-; CHECK-NOVFP-DAG: ldrh
-; CHECK-NOVFP-DAG: orr
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: ldrh
-; CHECK-NOVFP-DAG: ldrh
-; CHECK-NOVFP-DAG: ldrh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-; CHECK-NOVFP-DAG: strh
-
+; CHECK-ALL: ldrh
+; CHECK-ALL: ldrh
+; CHECK-ALL: ldrh
+; CHECK-ALL: ldrh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: mov
+; CHECK-ALL-DAG: ldrh
+; CHECK-ALL-DAG: orr
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: ldrh
+; CHECK-ALL-DAG: ldrh
+; CHECK-ALL-DAG: ldrh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
+; CHECK-ALL-DAG: strh
 ; CHECK-ALL: add sp, sp, #8
 define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 {
   %a = load half, half* %p, align 2