[PATCH] D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection

[Nirav Davé via llvm-commits]

Sure If no one objects I'll disable this for just the ARM target.

-Nirav

On Wed, Nov 29, 2017 at 12:23 PM, Evgeny Astigeevich via Phabricator <
reviews at reviews.llvm.org> wrote:

> eastig added a comment.
>
> Hi Nirav,
>
> Could you please revert the changes? They affected Arm targets (Thumb2
> code).
> The following sequence of stores:
>
>   MOVS     r0,#0xe5
>   STRB     r0,[r6,#0x1e5]
>   MOVS     r0,#0xe4
>   STRB     r0,[r6,#0x1e4]
>   MOVS     r0,#0xe6
>   STRB     r0,[r6,#0x1e6]
>   MOVS     r0,#0xe7
>   STRB     r0,[r6,#0x1e7]
>
> is optimised into
>
>   MVN      r0,#0x1b
>   STR      r0,[r6,#0x1e4]
>
> causing incorrect data to be written.
>
> We are working on a reproducer.
>
> Thanks,
> Evgeny Astigeevich
> The Arm Compiler Optimisation team
>
>
> Repository:
>   rL LLVM
>
> https://reviews.llvm.org/D33675
>
>
>
>
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