[PATCH] D40532: [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal()
Diana Picus via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 03:58:38 PST 2017
rovka added a subscriber: igorb.
rovka added a comment.
In https://reviews.llvm.org/D40532#938284, @dsanders wrote:
> I think GIM_CheckLiteralInt might have the same issue but I don't think there's any existing rules that would detect the problem. As far as I know X86 is the only user and only uses 0 and 1. We should probably change it to match GIM_CheckConstantInt if only for consistency. Do you agree?
That sounds like a good idea, and I think we can test with the MOV32r_1 pattern, which uses a -1. I think for something like this, it should select a MOV32r_1:
--- |
define i32 @const_i32_0() #0 {
ret i32 0
}
attributes #0 = { optsize "target-features"="-64bit-mode"}
...
---
name: const_i32_0
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
body: |
bb.1 (%ir-block.0):
%0(s32) = G_CONSTANT i32 -1
%eax = COPY %0(s32)
RET 0, implicit %eax
...
I'll let @igorb correct me if I'm wrong...
https://reviews.llvm.org/D40532
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