[PATCH] D39078: [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended
Sean Fertile via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 20:10:00 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL319289: [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended. (authored by sfertile).
Changed prior to commit:
https://reviews.llvm.org/D39078?vs=119540&id=124689#toc
Repository:
rL LLVM
https://reviews.llvm.org/D39078
Files:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/test/CodeGen/PowerPC/zext-and-cmp.ll
Index: llvm/trunk/test/CodeGen/PowerPC/zext-and-cmp.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/zext-and-cmp.ll
+++ llvm/trunk/test/CodeGen/PowerPC/zext-and-cmp.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Test that we recognize that an 'and' instruction that feeds a comparison
+; to zero can be simplifed by using the record form when one of its operands
+; is known to be zero extended.
+
+ at k = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind
+define signext i32 @cmplwi(i32* nocapture readonly %p, i32* nocapture readonly %q, i32 signext %j, i32 signext %r10) {
+entry:
+ %0 = load i32, i32* %q, align 4
+ %shl = shl i32 %0, %j
+ %1 = load i32, i32* %p, align 4
+ %and = and i32 %shl, %r10
+ %and1 = and i32 %and, %1
+ %tobool = icmp eq i32 %and1, 0
+ br i1 %tobool, label %cleanup, label %if.then
+
+if.then:
+ store i32 %j, i32* @k, align 4
+ br label %cleanup
+
+cleanup:
+ %retval.0 = phi i32 [ 0, %if.then ], [ 1, %entry ]
+ ret i32 %retval.0
+}
+
+; CHECK-LABEL: cmplwi:
+; CHECK: lwz [[T1:[0-9]+]], 0(3)
+; CHECK: and. {{[0-9]+}}, {{[0-9]+}}, [[T1]]
+; CHECK-NOT: cmplwi
+; CHECK-NEXT: beq 0,
Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2378,9 +2378,7 @@
}
// If all incoming values are sign-/zero-extended,
- // the output of AND, OR, ISEL or PHI is also sign-/zero-extended.
- case PPC::AND:
- case PPC::AND8:
+ // the output of OR, ISEL or PHI is also sign-/zero-extended.
case PPC::OR:
case PPC::OR8:
case PPC::ISEL:
@@ -2411,6 +2409,36 @@
return true;
}
+ // If at least one of the incoming values of an AND is zero extended
+ // then the output is also zero-extended. If both of the incoming values
+ // are sign-extended then the output is also sign extended.
+ case PPC::AND:
+ case PPC::AND8: {
+ if (Depth >= MAX_DEPTH)
+ return false;
+
+ assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
+
+ unsigned SrcReg1 = MI.getOperand(1).getReg();
+ unsigned SrcReg2 = MI.getOperand(2).getReg();
+
+ if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
+ !TargetRegisterInfo::isVirtualRegister(SrcReg2))
+ return false;
+
+ const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
+ const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
+ if (!MISrc1 || !MISrc2)
+ return false;
+
+ if(SignExt)
+ return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
+ isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ else
+ return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
+ isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ }
+
default:
break;
}
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