[PATCH] D40343: AMDGPU: Do not combine loads/store across physreg defs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:359
+        // tracking physreg defs and uses. This should only affect M0 in
+        // practice.
+        return false;
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nhaehnle wrote:
> arsenm wrote:
> > There could also be a call instruction, and the function may modify m0 or anything else
> To clarify, this means that we should bail out entirely when we encounter a call instruction, right?
I think this would just fall out naturally from physreg defs (although I guess you could have a void call that doesn't modify any visible registers), but you might need a call check


https://reviews.llvm.org/D40343