[llvm] r319203 - [InstCombine] auto-generate complete test checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 28 11:07:28 PST 2017
Author: spatel
Date: Tue Nov 28 11:07:28 2017
New Revision: 319203
URL: http://llvm.org/viewvc/llvm-project?rev=319203&view=rev
Log:
[InstCombine] auto-generate complete test checks; NFC
Modified:
llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
Modified: llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll?rev=319203&r1=319202&r2=319203&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll Tue Nov 28 11:07:28 2017
@@ -1,14 +1,16 @@
; RUN: opt -instcombine -S < %s | FileCheck %s
; <rdar://problem/8606771>
+define i32 @main(i32 %argc) {
; CHECK-LABEL: @main(
-define i32 @main(i32 %argc) nounwind ssp {
-entry:
+; CHECK-NEXT: [[TMP3151:%.*]] = trunc i32 %argc to i8
+; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[TMP3151]], 5
+; CHECK-NEXT: [[TMP4126:%.*]] = and i8 [[TMP1]], 64
+; CHECK-NEXT: [[TMP4127:%.*]] = xor i8 [[TMP4126]], 64
+; CHECK-NEXT: [[TMP4086:%.*]] = zext i8 [[TMP4127]] to i32
+; CHECK-NEXT: ret i32 [[TMP4086]]
+;
%tmp3151 = trunc i32 %argc to i8
-; CHECK: %0 = shl i8 %tmp3151, 5
-; CHECK: and i8 %0, 64
-; CHECK-NOT: shl
-; CHECK-NOT: shr
%tmp3161 = or i8 %tmp3151, -17
%tmp3162 = and i8 %tmp3151, 122
%tmp3163 = xor i8 %tmp3162, -17
@@ -18,14 +20,26 @@ entry:
%tmp4126 = lshr i8 %tmp4120, 7
%tmp4127 = mul i8 %tmp4126, 64
%tmp4086 = zext i8 %tmp4127 to i32
-; CHECK: ret i32
ret i32 %tmp4086
}
; rdar://8739316
+define i8 @foo(i8 %arg, i8 %arg1) {
; CHECK-LABEL: @foo(
-define i8 @foo(i8 %arg, i8 %arg1) nounwind {
-bb:
+; CHECK-NEXT: [[TMP:%.*]] = shl i8 %arg, 7
+; CHECK-NEXT: [[TMP2:%.*]] = and i8 %arg1, 84
+; CHECK-NEXT: [[TMP3:%.*]] = and i8 %arg1, -118
+; CHECK-NEXT: [[TMP4:%.*]] = and i8 %arg1, 33
+; CHECK-NEXT: [[TMP5:%.*]] = sub nsw i8 40, [[TMP2]]
+; CHECK-NEXT: [[TMP6:%.*]] = and i8 [[TMP5]], 84
+; CHECK-NEXT: [[TMP7:%.*]] = or i8 [[TMP4]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = xor i8 [[TMP]], [[TMP3]]
+; CHECK-NEXT: [[TMP9:%.*]] = or i8 [[TMP7]], [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i8 [[TMP8]], 7
+; CHECK-NEXT: [[TMP11:%.*]] = shl nuw nsw i8 [[TMP10]], 5
+; CHECK-NEXT: [[TMP12:%.*]] = xor i8 [[TMP11]], [[TMP9]]
+; CHECK-NEXT: ret i8 [[TMP12]]
+;
%tmp = shl i8 %arg, 7
%tmp2 = and i8 %arg1, 84
%tmp3 = and i8 %arg1, -118
@@ -37,10 +51,7 @@ bb:
%tmp9 = or i8 %tmp7, %tmp8
%tmp10 = lshr i8 %tmp8, 7
%tmp11 = shl i8 %tmp10, 5
-
-; CHECK: %tmp10 = lshr i8 %tmp8, 7
-; CHECK: %tmp11 = shl nuw nsw i8 %tmp10, 5
-
%tmp12 = xor i8 %tmp11, %tmp9
ret i8 %tmp12
}
+
Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll?rev=319203&r1=319202&r2=319203&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Tue Nov 28 11:07:28 2017
@@ -1,26 +1,33 @@
-; ModuleID = 'test1.c'
; RUN: opt -S -instcombine < %s | FileCheck %s
+
target triple = "x86_64-apple-macosx10.6.6"
-define zeroext i16 @foo1(i32 %on_off) nounwind uwtable ssp {
-entry:
+define zeroext i16 @foo1(i32 %on_off) {
+; CHECK-LABEL: @foo1(
+; CHECK-NEXT: [[ON_OFF_TR:%.*]] = trunc i32 %on_off to i16
+; CHECK-NEXT: [[TMP1:%.*]] = shl i16 [[ON_OFF_TR]], 1
+; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -2
+; CHECK-NEXT: ret i16 [[CONV]]
+;
%on_off.addr = alloca i32, align 4
%a = alloca i32, align 4
store i32 %on_off, i32* %on_off.addr, align 4
%tmp = load i32, i32* %on_off.addr, align 4
%sub = sub i32 1, %tmp
-; CHECK-NOT: mul i32
%mul = mul i32 %sub, -2
-; CHECK: shl
-; CHECK-NEXT: add
store i32 %mul, i32* %a, align 4
%tmp1 = load i32, i32* %a, align 4
%conv = trunc i32 %tmp1 to i16
ret i16 %conv
}
-define zeroext i16 @foo2(i32 %on_off, i32 %q) nounwind uwtable ssp {
-entry:
+define zeroext i16 @foo2(i32 %on_off, i32 %q) {
+; CHECK-LABEL: @foo2(
+; CHECK-NEXT: [[SUBA:%.*]] = sub i32 %on_off, %q
+; CHECK-NEXT: [[SUBA_TR:%.*]] = trunc i32 [[SUBA]] to i16
+; CHECK-NEXT: [[CONV:%.*]] = shl i16 [[SUBA_TR]], 2
+; CHECK-NEXT: ret i16 [[CONV]]
+;
%on_off.addr = alloca i32, align 4
%q.addr = alloca i32, align 4
%a = alloca i32, align 4
@@ -29,31 +36,29 @@ entry:
%tmp = load i32, i32* %q.addr, align 4
%tmp1 = load i32, i32* %on_off.addr, align 4
%sub = sub i32 %tmp, %tmp1
-; CHECK-NOT: mul i32
%mul = mul i32 %sub, -4
-; CHECK: sub i32
-; CHECK-NEXT: trunc i32
-; CHECK-NEXT: %conv = shl i16 %{{.*}}, 2
-; CHECK-NEXT: ret i16 %conv
store i32 %mul, i32* %a, align 4
%tmp2 = load i32, i32* %a, align 4
%conv = trunc i32 %tmp2 to i16
ret i16 %conv
}
-define zeroext i16 @foo3(i32 %on_off) nounwind uwtable ssp {
-entry:
+define zeroext i16 @foo3(i32 %on_off) {
+; CHECK-LABEL: @foo3(
+; CHECK-NEXT: [[ON_OFF_TR:%.*]] = trunc i32 %on_off to i16
+; CHECK-NEXT: [[TMP1:%.*]] = shl i16 [[ON_OFF_TR]], 2
+; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -28
+; CHECK-NEXT: ret i16 [[CONV]]
+;
%on_off.addr = alloca i32, align 4
%a = alloca i32, align 4
store i32 %on_off, i32* %on_off.addr, align 4
%tmp = load i32, i32* %on_off.addr, align 4
%sub = sub i32 7, %tmp
-; CHECK-NOT: mul i32
%mul = mul i32 %sub, -4
-; CHECK: shl
-; CHECK-NEXT: add
store i32 %mul, i32* %a, align 4
%tmp1 = load i32, i32* %a, align 4
%conv = trunc i32 %tmp1 to i16
ret i16 %conv
}
+
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